nvgpu:ps35: Clock domain changes

1. PMU interface changes
2. Split PS3.0 and PS3.5 into two dev init functions.
3. Split construct and pmu_data_init to two funcitons.
4. Fixing GV100 impact on PS3.5 changes

Change-Id: I46ba80325d4a249918edbe4cf868ddf47c778aa1
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1777739
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2 files changed, 60 insertions, 14 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/bios.h b/drivers/gpu/nvgpu/include/nvgpu/bios.h
index 0323dce4..10b220b7 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/bios.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/bios.h
@@ -171,6 +171,17 @@ struct vbios_clocks_table_1x_header {
         u16 cntr_sampling_periodms;
 } __packed;
 
+#define VBIOS_CLOCKS_TABLE_35_HEADER_SIZE_09 0x09
+struct vbios_clocks_table_35_header {
+        u8 version;
+        u8 header_size;
+        u8 entry_size;
+        u8 entry_count;
+        u8 clocks_hal;
+        u16 cntr_sampling_periodms;
+        u16 reference_window;
+} __packed;
+
 #define VBIOS_CLOCKS_TABLE_1X_ENTRY_SIZE_09                                 0x09
 struct vbios_clocks_table_1x_entry {
         u8 flags0;
@@ -179,6 +190,15 @@ struct vbios_clocks_table_1x_entry {
         u16 param2;
 } __packed;
 
+#define VBIOS_CLOCKS_TABLE_35_ENTRY_SIZE_11                                 0x0B
+struct vbios_clocks_table_35_entry {
+        u8 flags0;
+        u16 param0;
+        u32 param1;
+        u16 param2;
+        u16 param3;
+} __packed;
+
 #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_MASK                    0x1F
 #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_SHIFT                   0
 #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_FIXED                   0x00
@@ -212,6 +232,17 @@ struct vbios_clocks_table_1x_entry {
 #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_FALSE   0x00
 #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_TRUE    0x01
 
+#define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM2_PROG_PRE_VOLT_ORDERING_IDX_MASK 0xF
+#define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM2_PROG_PRE_VOLT_ORDERING_IDX_SHIFT 0
+
+#define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM2_PROG_POST_VOLT_ORDERING_IDX_MASK     0xF0
+#define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM2_PROG_POST_VOLT_ORDERING_IDX_SHIFT   4
+
+#define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM3_CLK_MONITOR_THRESHOLD_MIN_MASK  0xFF
+#define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM3_CLK_MONITOR_THRESHOLD_MIN_SHIFT  0
+#define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM3_CLK_MONITOR_THRESHOLD_MAX_MASK  0xFF00
+#define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM3_CLK_MONITOR_THRESHOLD_MAX_SHIFT 0x08
+
 #define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_HEADER_SIZE_08                              0x08
 struct vbios_clock_programming_table_1x_header {
         u8 version;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h
index cdab649e..b94db25c 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h
@@ -118,48 +118,63 @@ struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set {
         short freq_delta_min_mhz;
         short freq_delta_max_mhz;
         struct ctrl_clk_clk_delta deltas;
+};
+
+struct nv_pmu_clk_clk_domain_30_prog_boardobj_set {
+        struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super;
         u8 noise_unaware_ordering_index;
         u8 noise_aware_ordering_index;
 };
 
 struct nv_pmu_clk_clk_domain_3x_master_boardobj_set {
-        struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super;
         u8 rsvd;        /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */
         u32 slave_idxs_mask;
 };
 
+struct nv_pmu_clk_clk_domain_30_master_boardobj_set {
+        struct nv_pmu_clk_clk_domain_30_prog_boardobj_set super;
+        struct nv_pmu_clk_clk_domain_3x_master_boardobj_set master;
+};
+
+struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set {
+        u8 rsvd;        /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */
+        u8 master_idx;
+};
+
+struct nv_pmu_clk_clk_domain_30_slave_boardobj_set {
+        struct nv_pmu_clk_clk_domain_30_prog_boardobj_set super;
+        struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set slave;
+};
+
 struct nv_pmu_clk_clk_domain_35_prog_boardobj_set {
         struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super;
-        u8 rsvd;        /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */
-        u8 dummy;
+        u8 pre_volt_ordering_index;
+        u8 post_volt_ordering_index;
+        u8 clk_pos;
+        u8 clk_vf_curve_count;
 };
 
 struct nv_pmu_clk_clk_domain_35_master_boardobj_set {
         struct nv_pmu_clk_clk_domain_35_prog_boardobj_set super;
-        u8 rsvd;        /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */
+        struct nv_pmu_clk_clk_domain_3x_master_boardobj_set master;
         u32 master_slave_domains_grp_mask;
 };
 
 
-struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set {
-        struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super;
-        u8 rsvd;        /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */
-        u8 master_idx;
-};
-
 struct nv_pmu_clk_clk_domain_35_slave_boardobj_set {
         struct nv_pmu_clk_clk_domain_35_prog_boardobj_set super;
-        u8 rsvd;        /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */
-        u8 master_idx;
+        struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set slave;
 };
+
 union nv_pmu_clk_clk_domain_boardobj_set_union {
         struct nv_pmu_boardobj board_obj;
         struct nv_pmu_clk_clk_domain_boardobj_set super;
         struct nv_pmu_clk_clk_domain_3x_boardobj_set v3x;
         struct nv_pmu_clk_clk_domain_3x_fixed_boardobj_set v3x_fixed;
         struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set v3x_prog;
-        struct nv_pmu_clk_clk_domain_3x_master_boardobj_set v3x_master;
-        struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set v3x_slave;
+        struct nv_pmu_clk_clk_domain_30_prog_boardobj_set v30_prog;
+        struct nv_pmu_clk_clk_domain_30_master_boardobj_set v30_master;
+        struct nv_pmu_clk_clk_domain_30_slave_boardobj_set v30_slave;
         struct nv_pmu_clk_clk_domain_35_prog_boardobj_set v35_prog;
         struct nv_pmu_clk_clk_domain_35_master_boardobj_set v35_master;
         struct nv_pmu_clk_clk_domain_35_slave_boardobj_set v35_slave;