gpu: nvgpu: PMU code cleanup

-removed unsupported PMU f/w version defines &
corrected naming specific to chip
-removed unsupported PMU f/w version methods
which are not useful for existing ucode.
-removed unsupported PMU interface which are not
useful for existing ucode

Change-Id: I17933ff656f48a888e049d680f108b2ef7537439
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1643399
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

4 files changed, 0 insertions, 119 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h b/drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h
index 1622849a..71ecc24a 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h
@@ -41,12 +41,6 @@ struct falc_dma_addr {
         u8 dma_offset;
 };
 
-struct pmu_mem_v0 {
-        u32 dma_base;
-        u8  dma_offset;
-        u8  dma_idx;
-};
-
 struct pmu_mem_v1 {
         u32 dma_base;
         u8  dma_offset;
@@ -54,12 +48,6 @@ struct pmu_mem_v1 {
         u16 fb_size;
 };
 
-struct pmu_mem_v2 {
-        struct falc_dma_addr dma_addr;
-        u8  dma_idx;
-        u16 fb_size;
-};
-
 struct pmu_mem_desc_v0 {
         struct falc_u64 dma_addr;
         u16       dma_sizemax;
@@ -78,15 +66,6 @@ struct flcn_mem_desc_v0 {
 
 #define nv_flcn_mem_desc flcn_mem_desc_v0
 
-struct pmu_allocation_v0 {
-        u8 pad[3];
-        u8 fb_mem_use;
-        struct {
-                struct pmu_dmem dmem;
-                struct pmu_mem_v0 fb;
-        } alloc;
-};
-
 struct pmu_allocation_v1 {
         struct {
                 struct pmu_dmem dmem;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmu.h
index 5e9983b0..5e34abe6 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/pmu.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmu.h
@@ -269,14 +269,12 @@ struct pmu_sequence {
         u32 desc;
         struct pmu_msg *msg;
         union {
-                struct pmu_allocation_v0 in_v0;
                 struct pmu_allocation_v1 in_v1;
                 struct pmu_allocation_v2 in_v2;
                 struct pmu_allocation_v3 in_v3;
         };
         struct nvgpu_mem *in_mem;
         union {
-                struct pmu_allocation_v0 out_v0;
                 struct pmu_allocation_v1 out_v1;
                 struct pmu_allocation_v2 out_v2;
                 struct pmu_allocation_v3 out_v3;
@@ -351,7 +349,6 @@ struct nvgpu_pmu {
 
         union {
                 struct pmu_perfmon_counter_v2 perfmon_counter_v2;
-                struct pmu_perfmon_counter_v0 perfmon_counter_v0;
         };
         u32 perfmon_state_id[PMU_DOMAIN_GROUP_NUM];
 
@@ -371,9 +368,6 @@ struct nvgpu_pmu {
 
         bool zbc_ready;
         union {
-                struct pmu_cmdline_args_v0 args_v0;
-                struct pmu_cmdline_args_v1 args_v1;
-                struct pmu_cmdline_args_v2 args_v2;
                 struct pmu_cmdline_args_v3 args_v3;
                 struct pmu_cmdline_args_v4 args_v4;
                 struct pmu_cmdline_args_v5 args_v5;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h
index bcf4c8b6..91e89365 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h
@@ -44,15 +44,6 @@ enum {
         PMU_PERFMON_CMD_ID_INIT  = 2
 };
 
-struct pmu_perfmon_counter_v0 {
-        u8 index;
-        u8 flags;
-        u8 group_id;
-        u8 valid;
-        u16 upper_threshold; /* units of 0.01% */
-        u16 lower_threshold; /* units of 0.01% */
-};
-
 struct pmu_perfmon_counter_v2 {
         u8 index;
         u8 flags;
@@ -96,14 +87,6 @@ struct pmu_perfmon_cmd_start_v1 {
         struct pmu_allocation_v1 counter_alloc;
 };
 
-struct pmu_perfmon_cmd_start_v0 {
-        u8 cmd_type;
-        u8 group_id;
-        u8 state_id;
-        u8 flags;
-        struct pmu_allocation_v0 counter_alloc;
-};
-
 struct pmu_perfmon_cmd_stop {
         u8 cmd_type;
 };
@@ -141,26 +124,13 @@ struct pmu_perfmon_cmd_init_v1 {
         u16 sample_buffer;
 };
 
-struct pmu_perfmon_cmd_init_v0 {
-        u8 cmd_type;
-        u8 to_decrease_count;
-        u8 base_counter_id;
-        u32 sample_period_us;
-        struct pmu_allocation_v0 counter_alloc;
-        u8 num_counters;
-        u8 samples_in_moving_avg;
-        u16 sample_buffer;
-};
-
 struct pmu_perfmon_cmd {
         union {
                 u8 cmd_type;
-                struct pmu_perfmon_cmd_start_v0 start_v0;
                 struct pmu_perfmon_cmd_start_v1 start_v1;
                 struct pmu_perfmon_cmd_start_v2 start_v2;
                 struct pmu_perfmon_cmd_start_v3 start_v3;
                 struct pmu_perfmon_cmd_stop stop;
-                struct pmu_perfmon_cmd_init_v0 init_v0;
                 struct pmu_perfmon_cmd_init_v1 init_v1;
                 struct pmu_perfmon_cmd_init_v2 init_v2;
                 struct pmu_perfmon_cmd_init_v3 init_v3;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h
index 91ef1bda..8e38db31 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h
@@ -26,33 +26,6 @@
 #include "gpmuif_cmn.h"
 
 /* Make sure size of this structure is a multiple of 4 bytes */
-struct pmu_cmdline_args_v0 {
-        u32 cpu_freq_hz;
-        u32 falc_trace_size;
-        u32 falc_trace_dma_base;
-        u32 falc_trace_dma_idx;
-        struct pmu_mem_v0 gc6_ctx;
-};
-
-struct pmu_cmdline_args_v1 {
-        u32 cpu_freq_hz;
-        u32 falc_trace_size;
-        u32 falc_trace_dma_base;
-        u32 falc_trace_dma_idx;
-        u8 secure_mode;
-        struct pmu_mem_v1 gc6_ctx;
-};
-
-struct pmu_cmdline_args_v2 {
-        u32 cpu_freq_hz;
-        u32 falc_trace_size;
-        u32 falc_trace_dma_base;
-        u32 falc_trace_dma_idx;
-        u8 secure_mode;
-        u8 raise_priv_sec;
-        struct pmu_mem_v1 gc6_ctx;
-};
-
 struct pmu_cmdline_args_v3 {
         u32 reserved;
         u32 cpu_freq_hz;
@@ -118,21 +91,6 @@ enum {
         PMU_INIT_MSG_TYPE_PMU_INIT = 0,
 };
 
-struct pmu_init_msg_pmu_v0 {
-        u8 msg_type;
-        u8 pad;
-
-        struct {
-                u16 size;
-                u16 offset;
-                u8  index;
-                u8  pad;
-        } queue_info[PMU_QUEUE_COUNT];
-
-        u16 sw_managed_area_offset;
-        u16 sw_managed_area_size;
-};
-
 struct pmu_init_msg_pmu_v1 {
         u8 msg_type;
         u8 pad;
@@ -148,22 +106,6 @@ struct pmu_init_msg_pmu_v1 {
         u16 sw_managed_area_offset;
         u16 sw_managed_area_size;
 };
-struct pmu_init_msg_pmu_v2 {
-        u8 msg_type;
-        u8 pad;
-        u16  os_debug_entry_point;
-
-        struct {
-                u16 size;
-                u16 offset;
-                u8  index;
-                u8  pad;
-        } queue_info[PMU_QUEUE_COUNT];
-
-        u16 sw_managed_area_offset;
-        u16 sw_managed_area_size;
-        u8 dummy[18];
-};
 
 #define PMU_QUEUE_COUNT_FOR_V4 5
 #define PMU_QUEUE_COUNT_FOR_V3 3
@@ -200,9 +142,7 @@ struct pmu_init_msg_pmu_v4 {
 };
 
 union pmu_init_msg_pmu {
-        struct pmu_init_msg_pmu_v0 v0;
         struct pmu_init_msg_pmu_v1 v1;
-        struct pmu_init_msg_pmu_v2 v2;
         struct pmu_init_msg_pmu_v3 v3;
         struct pmu_init_msg_pmu_v4 v4;
 };
@@ -211,8 +151,6 @@ struct pmu_init_msg {
         union {
                 u8 msg_type;
                 struct pmu_init_msg_pmu_v1 pmu_init_v1;
-                struct pmu_init_msg_pmu_v0 pmu_init_v0;
-                struct pmu_init_msg_pmu_v2 pmu_init_v2;
                 struct pmu_init_msg_pmu_v3 pmu_init_v3;
                 struct pmu_init_msg_pmu_v4 pmu_init_v4;
         };