gpu: nvgpu: gv100: BOOTSTRAP_GR_FALCONS using RPC

- Created nv_pmu_rpc_struct_acr_bootstrap_gr_falcons struct
- gv100_load_falcon_ucode() function to bootstrap GR
flacons using RPC, wait for INIT_WPR_REGION before
creating & executing BOOTSTRAP_GR_FALCONS RPC.
- Added code to handle BOOTSTRAP_GR_FALCONS ack in
RPC handler

Change-Id: If70dc75bb2789970382853fb001d970a346b2915
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1613316
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 25 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_acr.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_acr.h
index bc3b1056..c1a4b360 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_acr.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_acr.h
@@ -131,4 +131,29 @@ struct nv_pmu_rpc_struct_acr_init_wpr_region {
         u32 scratch[1];
 };
 
+/*
+ * structure that holds data used to
+ * execute BOOTSTRAP_GR_FALCONS RPC.
+ */
+struct nv_pmu_rpc_struct_acr_bootstrap_gr_falcons {
+        /*[IN/OUT] Must be first field in RPC structure */
+        struct nv_pmu_rpc_header hdr;
+        /* [IN] Mask of falcon IDs @ref LSF_FALCON_ID_<XYZ> */
+        u32  falcon_id_mask;
+        /*
+         * [IN] Boostrapping flags @ref
+         * PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_<XYZ>
+         */
+        u32 flags;
+        /* [IN] Indicate whether the particular falon uses VA */
+        u32  falcon_va_mask;
+        /*
+         * [IN] WPR Base Address in VA. The Inst Block containing
+         * this VA should be bound to both PMU and GR falcons
+         * during the falcon boot
+         */
+        struct falc_u64  wpr_base_virtual;
+        u32  scratch[1];
+};
+
 #endif /* _GPMUIFACR_H_ */