gpu: nvgpu: add clock freq controller support

JIRA DNVGPU-170

1) Add clock frequency controller VBIOS structure definitions

2) Parse VBIOS tables and build boardobj structures for clock frequency
controller.

3) send clock frequency controller data structures to PMU

4) implement public function to send load/unload command to pmu
to enable/disable clock frequency controller support

Change-Id: I2f37f6a94f342b6fcc71bb802e6e440a0a454486
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1248209
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
(cherry picked from commit ed3e27933f21e10b3d7a5257f1b751526945bd07)
Reviewed-on: http://git-master/r/1270897
GVS: Gerrit_Virtual_Submit

1 files changed, 83 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/include/bios.h b/drivers/gpu/nvgpu/include/bios.h
index 02991db9..f3939d14 100644
--- a/drivers/gpu/nvgpu/include/bios.h
+++ b/drivers/gpu/nvgpu/include/bios.h
@@ -842,4 +842,87 @@ struct therm_channel_1x_entry {
 #define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM1_DEVICE_PROVIDER_INDEX_MASK  0xFF
 #define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM1_DEVICE_PROVIDER_INDEX_SHIFT    0
 
+/* Frequency Controller Table */
+struct vbios_fct_1x_header {
+        u8 version;
+        u8 header_size;
+        u8 entry_size;
+        u8 entry_count;
+        u16 sampling_period_ms;
+} __packed;
+
+struct vbios_fct_1x_entry {
+        u8 flags0;
+        u8 clk_domain_idx;
+        u16 param0;
+        u16 param1;
+        u32 param2;
+        u32 param3;
+        u32 param4;
+        u32 param5;
+        u32 param6;
+        u32 param7;
+        u32 param8;
+} __packed;
+
+#define NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE_MASK GENMASK(3, 0)
+#define NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE_SHIFT 0
+#define NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE_DISABLED 0x0
+#define NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE_PI       0x1
+
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_MASK GENMASK(7, 0)
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_SHIFT 0
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_SYS   0x00
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_LTC   0x01
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_XBAR  0x02
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC0  0x03
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC1  0x04
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC2  0x05
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC3  0x06
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC4  0x07
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC5  0x08
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPCS  0x09
+
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_MASK GENMASK(9, 8)
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_SHIFT 8
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_BCAST 0x0
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_MIN   0x1
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_MAX   0x2
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_AVG   0x3
+
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_SLOWDOWN_PCT_MIN_MASK GENMASK(7, 0)
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_SLOWDOWN_PCT_MIN_SHIFT 0
+
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON_MASK GENMASK(8, 8)
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON_SHIFT 8
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON_NO  0x0
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON_YES 0x1
+
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM2_PROP_GAIN_MASK GENMASK(31, 0)
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM2_PROP_GAIN_SHIFT 0
+
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM3_INTEG_GAIN_MASK GENMASK(31, 0)
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM3_INTEG_GAIN_SHIFT 0
+
+
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM4_INTEG_DECAY_MASK GENMASK(31, 0)
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM4_INTEG_DECAY_SHIFT 0
+
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM5_VOLT_DELTA_MIN_MASK GENMASK(31, 0)
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM5_VOLT_DELTA_MIN_SHIFT 0
+
+
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM6_VOLT_DELTA_MAX_MASK GENMASK(31, 0)
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM6_VOLT_DELTA_MAX_SHIFT 0
+
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VF_MASK GENMASK(15, 0)
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VF_SHIFT 0
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VMIN_MASK GENMASK(31, 16)
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VMIN_SHIFT 16
+
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_POS_MASK GENMASK(15, 0)
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_POS_SHIFT 0
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_NEG_MASK GENMASK(31, 16)
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_NEG_SHIFT 16
+
 #endif