Revert "Revert "gpu: nvgpu: Get coherency on gv100 + NVLINK working""

This reverts commit 5a35a95654d561fce09a3b9abf6b82bb7a29d74b.

JIRA EVLR-2333

Change-Id: I923c32496c343d39d34f6d406c38a9f6ce7dc6e0
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1667167
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2 files changed, 19 insertions, 8 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/enabled.h b/drivers/gpu/nvgpu/include/nvgpu/enabled.h
index a3d9df24..24748a19 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/enabled.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/enabled.h
@@ -75,8 +75,8 @@ struct gk20a;
 #define NVGPU_SUPPORT_MAP_DIRECT_KIND_CTRL      24
 /* Support batch mapping */
 #define NVGPU_SUPPORT_MAP_BUFFER_BATCH          25
-/* Support DMA coherence */
-#define NVGPU_DMA_COHERENT                      26
+/* Use coherent aperture for sysmem. */
+#define NVGPU_USE_COHERENT_SYSMEM               26
 /* Use physical scatter tables instead of IOMMU */
 #define NVGPU_MM_USE_PHYSICAL_SG                27
 
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h
index 04e947e0..373c3eef 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h
@@ -25,6 +25,7 @@
 
 #include <nvgpu/types.h>
 #include <nvgpu/list.h>
+#include <nvgpu/enabled.h>
 
 #ifdef __KERNEL__
 #include <nvgpu/linux/nvgpu_mem.h>
@@ -51,6 +52,10 @@ struct nvgpu_page_alloc;
 enum nvgpu_aperture {
         APERTURE_INVALID = 0, /* unallocated or N/A */
         APERTURE_SYSMEM,
+
+         /* Don't use directly. Use APERTURE_SYSMEM, this is used internally. */
+        __APERTURE_SYSMEM_COH,
+
         APERTURE_VIDMEM
 };
 
@@ -195,12 +200,18 @@ nvgpu_mem_from_clear_list_entry(struct nvgpu_list_node *node)
                                             clear_list_entry));
 };
 
-static inline const char *nvgpu_aperture_str(enum nvgpu_aperture aperture)
+static inline const char *nvgpu_aperture_str(struct gk20a *g,
+                                             enum nvgpu_aperture aperture)
 {
         switch (aperture) {
-                case APERTURE_INVALID: return "INVAL";
-                case APERTURE_SYSMEM:  return "SYSMEM";
-                case APERTURE_VIDMEM:  return "VIDMEM";
+        case APERTURE_INVALID:
+                return "INVAL";
+        case APERTURE_SYSMEM:
+                return "SYSMEM";
+        case __APERTURE_SYSMEM_COH:
+                return "SYSCOH";
+        case APERTURE_VIDMEM:
+                return "VIDMEM";
         };
         return "UNKNOWN";
 }
@@ -332,9 +343,9 @@ u64 nvgpu_mem_get_addr(struct gk20a *g, struct nvgpu_mem *mem);
 u64 nvgpu_mem_get_phys_addr(struct gk20a *g, struct nvgpu_mem *mem);
 
 u32 __nvgpu_aperture_mask(struct gk20a *g, enum nvgpu_aperture aperture,
-                u32 sysmem_mask, u32 vidmem_mask);
+                u32 sysmem_mask, u32 sysmem_coh_mask, u32 vidmem_mask);
 u32 nvgpu_aperture_mask(struct gk20a *g, struct nvgpu_mem *mem,
-                u32 sysmem_mask, u32 vidmem_mask);
+                u32 sysmem_mask, u32 sysmem_coh_mask, u32 vidmem_mask);
 
 u64 nvgpu_mem_iommu_translate(struct gk20a *g, u64 phys);