diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2017-01-31 10:09:21 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-02-08 00:53:44 -0500 |
commit | 8522004c00264646feeb30ede3214f46ddbea04d (patch) | |
tree | 920c82db4d0517111269a2b50580734bb323dab3 /drivers/gpu/nvgpu/include | |
parent | 02190c7597d3b1a04ebcbc746b41f949ab699a18 (diff) |
gpu: nvgpu: Falcon-controller interface update
Moved falcon-controller common interface code
from pmu_common.h to flcnif_cmn.h file.
Interfaces are common for falcons irrespective
of F/W on falcon controllers
Jira NVGPU-19
Change-Id: Iad11b2fade8cf6716888773b2b1c23919cbcc07b
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1296695
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h | 131 |
1 files changed, 131 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h b/drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h new file mode 100644 index 00000000..9d11e0ed --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h | |||
@@ -0,0 +1,131 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | #ifndef __FLCNIFCMN_H__ | ||
15 | #define __FLCNIFCMN_H__ | ||
16 | |||
17 | #define PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED 0 | ||
18 | |||
19 | struct falc_u64 { | ||
20 | u32 lo; | ||
21 | u32 hi; | ||
22 | }; | ||
23 | |||
24 | struct falc_dma_addr { | ||
25 | u32 dma_base; | ||
26 | /* | ||
27 | * dma_base1 is 9-bit MSB for FB Base | ||
28 | * address for the transfer in FB after | ||
29 | * address using 49b FB address | ||
30 | */ | ||
31 | u16 dma_base1; | ||
32 | u8 dma_offset; | ||
33 | }; | ||
34 | |||
35 | struct pmu_mem_v0 { | ||
36 | u32 dma_base; | ||
37 | u8 dma_offset; | ||
38 | u8 dma_idx; | ||
39 | }; | ||
40 | |||
41 | struct pmu_mem_v1 { | ||
42 | u32 dma_base; | ||
43 | u8 dma_offset; | ||
44 | u8 dma_idx; | ||
45 | u16 fb_size; | ||
46 | }; | ||
47 | |||
48 | struct pmu_mem_v2 { | ||
49 | struct falc_dma_addr dma_addr; | ||
50 | u8 dma_idx; | ||
51 | u16 fb_size; | ||
52 | }; | ||
53 | |||
54 | struct pmu_mem_desc_v0 { | ||
55 | struct falc_u64 dma_addr; | ||
56 | u16 dma_sizemax; | ||
57 | u8 dma_idx; | ||
58 | }; | ||
59 | |||
60 | struct pmu_dmem { | ||
61 | u16 size; | ||
62 | u32 offset; | ||
63 | }; | ||
64 | |||
65 | struct flcn_mem_desc_v0 { | ||
66 | struct falc_u64 address; | ||
67 | u32 params; | ||
68 | }; | ||
69 | |||
70 | #define nv_flcn_mem_desc flcn_mem_desc_v0 | ||
71 | |||
72 | struct pmu_allocation_v0 { | ||
73 | u8 pad[3]; | ||
74 | u8 fb_mem_use; | ||
75 | struct { | ||
76 | struct pmu_dmem dmem; | ||
77 | struct pmu_mem_v0 fb; | ||
78 | } alloc; | ||
79 | }; | ||
80 | |||
81 | struct pmu_allocation_v1 { | ||
82 | struct { | ||
83 | struct pmu_dmem dmem; | ||
84 | struct pmu_mem_v1 fb; | ||
85 | } alloc; | ||
86 | }; | ||
87 | |||
88 | struct pmu_allocation_v2 { | ||
89 | struct { | ||
90 | struct pmu_dmem dmem; | ||
91 | struct pmu_mem_desc_v0 fb; | ||
92 | } alloc; | ||
93 | }; | ||
94 | |||
95 | struct pmu_allocation_v3 { | ||
96 | struct { | ||
97 | struct pmu_dmem dmem; | ||
98 | struct flcn_mem_desc_v0 fb; | ||
99 | } alloc; | ||
100 | }; | ||
101 | |||
102 | #define nv_pmu_allocation pmu_allocation_v3 | ||
103 | |||
104 | struct pmu_hdr { | ||
105 | u8 unit_id; | ||
106 | u8 size; | ||
107 | u8 ctrl_flags; | ||
108 | u8 seq_id; | ||
109 | }; | ||
110 | |||
111 | #define PMU_MSG_HDR_SIZE sizeof(struct pmu_hdr) | ||
112 | #define PMU_CMD_HDR_SIZE sizeof(struct pmu_hdr) | ||
113 | |||
114 | #define nv_pmu_hdr pmu_hdr | ||
115 | typedef u8 flcn_status; | ||
116 | |||
117 | #define PMU_DMEM_ALLOC_ALIGNMENT (4) | ||
118 | #define PMU_DMEM_ALIGNMENT (4) | ||
119 | |||
120 | #define PMU_CMD_FLAGS_PMU_MASK (0xF0) | ||
121 | |||
122 | #define PMU_CMD_FLAGS_STATUS BIT(0) | ||
123 | #define PMU_CMD_FLAGS_INTR BIT(1) | ||
124 | #define PMU_CMD_FLAGS_EVENT BIT(2) | ||
125 | #define PMU_CMD_FLAGS_WATERMARK BIT(3) | ||
126 | |||
127 | #define ALIGN_UP(v, gran) (((v) + ((gran) - 1)) & ~((gran)-1)) | ||
128 | |||
129 | #define NV_UNSIGNED_ROUNDED_DIV(a, b) (((a) + ((b) / 2)) / (b)) | ||
130 | |||
131 | #endif /* _FLCNIFCMN_H_*/ | ||