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authorabsalam <absalam@nvidia.com>2018-09-20 02:51:33 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-09-27 07:54:44 -0400
commit850f2ad8ada4f4c2c753644f387d75e6d75ac28b (patch)
treee2ebdf3379b5900116ed6d6dd2013a514f2e4ced /drivers/gpu/nvgpu/include
parent19a27b99608fe0d0752b12f694c65e38af1c0660 (diff)
gpu: nvgpu:Add sysfs node for GV100 clocks
Creates sysfs nodes to read clk freq on GV100 Following sysfs nodes are created: gpcclk,xbarclk,sysclk Uses default clock source and counters for measurement Bug 200446261 Change-Id: I6903ba77fbe34e3f486f4b663e70eab4e7c5d662 Signed-off-by: absalam <absalam@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1828030 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_trim_gv100.h48
1 files changed, 48 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_trim_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_trim_gv100.h
index 9e7ceaff..f1b6da28 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_trim_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_trim_gv100.h
@@ -196,4 +196,52 @@ static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_onesrcclk_f(void)
196{ 196{
197 return 0x3U; 197 return 0x3U;
198} 198}
199static inline u32 trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_r(void)
200{
201 return 0x00132a70U;
202}
203static inline u32 trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_source_gpcclk_f(void)
204{
205 return 0x10000000U;
206}
207static inline u32 trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cnt0_r(void)
208{
209 return 0x00132a74U;
210}
211static inline u32 trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cnt1_r(void)
212{
213 return 0x00132a78U;
214}
215static inline u32 trim_sys_nafll_fr_clk_cntr_xbarclk_cfg_r(void)
216{
217 return 0x00136470U;
218}
219static inline u32 trim_sys_nafll_fr_clk_cntr_xbarclk_cfg_source_xbarclk_f(void)
220{
221 return 0x10000000U;
222}
223static inline u32 trim_sys_nafll_fr_clk_cntr_xbarclk_cntr0_r(void)
224{
225 return 0x00136474U;
226}
227static inline u32 trim_sys_nafll_fr_clk_cntr_xbarclk_cntr1_r(void)
228{
229 return 0x00136478U;
230}
231static inline u32 trim_sys_fr_clk_cntr_sysclk_cfg_r(void)
232{
233 return 0x0013762cU;
234}
235static inline u32 trim_sys_fr_clk_cntr_sysclk_cfg_source_sysclk_f(void)
236{
237 return 0x20000000U;
238}
239static inline u32 trim_sys_fr_clk_cntr_sysclk_cntr0_r(void)
240{
241 return 0x00137630U;
242}
243static inline u32 trim_sys_fr_clk_cntr_sysclk_cntr1_r(void)
244{
245 return 0x00137634U;
246}
199#endif 247#endif