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authorMahantesh Kumbar <mkumbar@nvidia.com>2018-02-27 04:22:19 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2018-03-13 17:09:52 -0400
commit76ad9e8366f5c73d1ea47d54cea043f8cd9fa23e (patch)
tree6ca5a8ba117568252a1e75a28542d405a250e49e /drivers/gpu/nvgpu/include
parent1d986dc33eae7cb56cd0a1beded5ba858f0535b9 (diff)
gpu: nvgpu: Updated RPC to support copyback & callback
- Updated & added new parameter "bool is_copy_back" to nvgpu_pmu_rpc_execute() to support copy back processed RPC request from PMU to caller by passing parameter value true & this blocks method till it receives ACK from PMU for requested RPC. - Added "struct rpc_handler_payload" to hold info required for RPC handler like RPC buff address & clear memory if copy back is not requested. - Added define PMU_RPC_EXECUTE_CPB to support to copy back processed RPC request from PMU to caller. - Updated RPC callback handler support, crated memory & assigned default handler if callback is not requested else use callback parameters data to request to PMU. - Added define PMU_RPC_EXECUTE_CB to support callback - Updated pmu_wait_message_cond(), restricted condition check to 8-bit instead 32-bit condition check. Change-Id: Ic05289b074954979fd0102daf5ab806bf1f07b62 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1664962 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/pmu.h40
1 files changed, 37 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmu.h
index 76a54fa1..507b8133 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/pmu.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmu.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -154,12 +154,45 @@ enum {
154 \ 154 \
155 _stat = nvgpu_pmu_rpc_execute(_pmu, &((_prpc)->hdr), \ 155 _stat = nvgpu_pmu_rpc_execute(_pmu, &((_prpc)->hdr), \
156 (sizeof(*(_prpc)) - sizeof((_prpc)->scratch)),\ 156 (sizeof(*(_prpc)) - sizeof((_prpc)->scratch)),\
157 (_size), NULL, NULL); \ 157 (_size), NULL, NULL, false); \
158 } while (0)
159
160/* RPC blocking call to copy back data from PMU to _prpc */
161#define PMU_RPC_EXECUTE_CPB(_stat, _pmu, _unit, _func, _prpc, _size)\
162 do { \
163 memset(&((_prpc)->hdr), 0, sizeof((_prpc)->hdr));\
164 \
165 (_prpc)->hdr.unit_id = PMU_UNIT_##_unit; \
166 (_prpc)->hdr.function = NV_PMU_RPC_ID_##_unit##_##_func;\
167 (_prpc)->hdr.flags = 0x0; \
168 \
169 _stat = nvgpu_pmu_rpc_execute(_pmu, &((_prpc)->hdr), \
170 (sizeof(*(_prpc)) - sizeof((_prpc)->scratch)),\
171 (_size), NULL, NULL, true); \
172 } while (0)
173
174/* RPC non-blocking with call_back handler option */
175#define PMU_RPC_EXECUTE_CB(_stat, _pmu, _unit, _func, _prpc, _size, _cb, _cbp)\
176 do { \
177 memset(&((_prpc)->hdr), 0, sizeof((_prpc)->hdr));\
178 \
179 (_prpc)->hdr.unit_id = PMU_UNIT_##_unit; \
180 (_prpc)->hdr.function = NV_PMU_RPC_ID_##_unit##_##_func;\
181 (_prpc)->hdr.flags = 0x0; \
182 \
183 _stat = nvgpu_pmu_rpc_execute(_pmu, &((_prpc)->hdr), \
184 (sizeof(*(_prpc)) - sizeof((_prpc)->scratch)),\
185 (_size), _cb, _cbp, false); \
158 } while (0) 186 } while (0)
159 187
160typedef void (*pmu_callback)(struct gk20a *, struct pmu_msg *, void *, u32, 188typedef void (*pmu_callback)(struct gk20a *, struct pmu_msg *, void *, u32,
161 u32); 189 u32);
162 190
191struct rpc_handler_payload {
192 void *rpc_buff;
193 bool is_mem_free_set;
194};
195
163struct pmu_rpc_desc { 196struct pmu_rpc_desc {
164 void *prpc; 197 void *prpc;
165 u16 size_rpc; 198 u16 size_rpc;
@@ -500,6 +533,7 @@ bool nvgpu_find_hex_in_string(char *strings, struct gk20a *g, u32 *hex_pos);
500 533
501/* PMU RPC */ 534/* PMU RPC */
502int nvgpu_pmu_rpc_execute(struct nvgpu_pmu *pmu, struct nv_pmu_rpc_header *rpc, 535int nvgpu_pmu_rpc_execute(struct nvgpu_pmu *pmu, struct nv_pmu_rpc_header *rpc,
503 u16 size_rpc, u16 size_scratch, pmu_callback callback, void *cb_param); 536 u16 size_rpc, u16 size_scratch, pmu_callback callback, void *cb_param,
537 bool is_copy_back);
504 538
505#endif /* __NVGPU_PMU_H__ */ 539#endif /* __NVGPU_PMU_H__ */