diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2018-01-19 05:18:48 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-01-25 17:24:15 -0500 |
commit | 758dac5567d3e514ea038d532b7fd86cec83a961 (patch) | |
tree | 8c6d9ec961215dafeb37668f3394905411f8f564 /drivers/gpu/nvgpu/include | |
parent | a63e7151172d53024c8057c90fda06124d34a618 (diff) |
gpu: nvgpu: gv100: PMU f/w update
-Added new version of pmu init msg "pmu_init_msg_pmu_v5"
-created methods to support new pmu init message parameter
read based on f/w version for below ops.
.get_pmu_msg_pmu_init_msg_ptr
.get_pmu_init_msg_pmu_sw_mg_off
.get_pmu_init_msg_pmu_sw_mg_size
-Corrected PMU_DMEM_ALLOC_ALIGNMENT value to 32 bit
to allocate PMU DMEM space for nvgpu
-Updated PMU version of GV100/APP_VERSION_BIGGPU
to 23440730 & PMU ucode CL is
https://git-master.nvidia.com/r/#/c/1642432/
Change-Id: Ib1e0197b5f3a229a601e810c9c0d93f05b9d69e7
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1642229
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h | 20 |
2 files changed, 21 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h b/drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h index 71ecc24a..d146cac7 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h +++ b/drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -102,7 +102,7 @@ struct pmu_hdr { | |||
102 | #define nv_pmu_hdr pmu_hdr | 102 | #define nv_pmu_hdr pmu_hdr |
103 | typedef u8 flcn_status; | 103 | typedef u8 flcn_status; |
104 | 104 | ||
105 | #define PMU_DMEM_ALLOC_ALIGNMENT (4) | 105 | #define PMU_DMEM_ALLOC_ALIGNMENT (32) |
106 | #define PMU_DMEM_ALIGNMENT (4) | 106 | #define PMU_DMEM_ALIGNMENT (4) |
107 | 107 | ||
108 | #define PMU_CMD_FLAGS_PMU_MASK (0xF0) | 108 | #define PMU_CMD_FLAGS_PMU_MASK (0xF0) |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h index 8e38db31..5f718dc6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -141,10 +141,27 @@ struct pmu_init_msg_pmu_v4 { | |||
141 | u8 dummy[18]; | 141 | u8 dummy[18]; |
142 | }; | 142 | }; |
143 | 143 | ||
144 | struct pmu_init_msg_pmu_v5 { | ||
145 | u8 msg_type; | ||
146 | u8 flcn_status; | ||
147 | u8 queue_index[PMU_QUEUE_COUNT_FOR_V4]; | ||
148 | u16 queue_size[PMU_QUEUE_COUNT_FOR_V4]; | ||
149 | u16 queue_offset; | ||
150 | |||
151 | u16 sw_managed_area_offset; | ||
152 | u16 sw_managed_area_size; | ||
153 | |||
154 | u16 os_debug_entry_point; | ||
155 | |||
156 | u8 dummy[18]; | ||
157 | u8 pad; | ||
158 | }; | ||
159 | |||
144 | union pmu_init_msg_pmu { | 160 | union pmu_init_msg_pmu { |
145 | struct pmu_init_msg_pmu_v1 v1; | 161 | struct pmu_init_msg_pmu_v1 v1; |
146 | struct pmu_init_msg_pmu_v3 v3; | 162 | struct pmu_init_msg_pmu_v3 v3; |
147 | struct pmu_init_msg_pmu_v4 v4; | 163 | struct pmu_init_msg_pmu_v4 v4; |
164 | struct pmu_init_msg_pmu_v5 v5; | ||
148 | }; | 165 | }; |
149 | 166 | ||
150 | struct pmu_init_msg { | 167 | struct pmu_init_msg { |
@@ -153,6 +170,7 @@ struct pmu_init_msg { | |||
153 | struct pmu_init_msg_pmu_v1 pmu_init_v1; | 170 | struct pmu_init_msg_pmu_v1 pmu_init_v1; |
154 | struct pmu_init_msg_pmu_v3 pmu_init_v3; | 171 | struct pmu_init_msg_pmu_v3 pmu_init_v3; |
155 | struct pmu_init_msg_pmu_v4 pmu_init_v4; | 172 | struct pmu_init_msg_pmu_v4 pmu_init_v4; |
173 | struct pmu_init_msg_pmu_v5 pmu_init_v5; | ||
156 | }; | 174 | }; |
157 | }; | 175 | }; |
158 | 176 | ||