gpu: nvgpu: gv100: INIT WPR region using RPC

- Created nv_pmu_rpc_struct_acr_init_wpr_region struct
- Function gv100_pmu_init_acr() to create & execute
 INIT_WPR_REGION using RPC.
- Updated gv100 HAL .init_wpr_region to point
 to gv100_pmu_init_acr()
- Added code to handle INIT_WPR_REGION ack in
RPC handler.

Change-Id: I699fa945790689e5f24ad5d3de022efb458662e0
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1613290
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 22 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_acr.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_acr.h
index 2d31207f..bc3b1056 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_acr.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_acr.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -110,4 +110,25 @@ struct pmu_acr_msg {
         };
 };
 
+/* ACR RPC */
+#define NV_PMU_RPC_ID_ACR_INIT_WPR_REGION      0x00
+#define NV_PMU_RPC_ID_ACR_WRITE_CBC_BASE       0x01
+#define NV_PMU_RPC_ID_ACR_BOOTSTRAP_FALCON     0x02
+#define NV_PMU_RPC_ID_ACR_BOOTSTRAP_GR_FALCONS 0x03
+#define NV_PMU_RPC_ID_ACR__COUNT               0x04
+
+/*
+ * structure that holds data used
+ * to execute INIT_WPR_REGION RPC.
+ */
+struct nv_pmu_rpc_struct_acr_init_wpr_region {
+        /*[IN/OUT] Must be first field in RPC structure */
+        struct nv_pmu_rpc_header hdr;
+        /*[IN] ACR region ID of WPR region */
+        u32 wpr_regionId;
+        /* [IN] WPR offset from startAddress */
+        u32 wpr_offset;
+        u32 scratch[1];
+};
+
 #endif /* _GPMUIFACR_H_ */