diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-07-08 18:51:17 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-07-17 05:35:56 -0400 |
commit | 68b65f642ab49e8d30a17da04c053673e49e6d24 (patch) | |
tree | c7e6542ddcd7a654ed0aafbc9661fc29a617f825 /drivers/gpu/nvgpu/include | |
parent | 81274038a4ac4404d4697cf54278da0a5154f353 (diff) |
gpu: nvgpu: gv11b: h/w header updated for CL 38810810
H/w header updates for FPGA SNAP_0617
Change-Id: I6d3fe0b5b36de5999b09b9aa65e6dde2817634b5
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1515766
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h | 122 |
2 files changed, 125 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h index bd2f628c..e98c9f76 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h | |||
@@ -266,10 +266,6 @@ static inline u32 fifo_intr_sched_error_code_f(u32 v) | |||
266 | { | 266 | { |
267 | return (v & 0xff) << 0; | 267 | return (v & 0xff) << 0; |
268 | } | 268 | } |
269 | static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void) | ||
270 | { | ||
271 | return 0x0000000a; | ||
272 | } | ||
273 | static inline u32 fifo_intr_chsw_error_r(void) | 269 | static inline u32 fifo_intr_chsw_error_r(void) |
274 | { | 270 | { |
275 | return 0x0000256c; | 271 | return 0x0000256c; |
@@ -308,7 +304,7 @@ static inline u32 fifo_intr_ctxsw_timeout_info__size_1_v(void) | |||
308 | } | 304 | } |
309 | static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_v(u32 r) | 305 | static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_v(u32 r) |
310 | { | 306 | { |
311 | return (r >> 0) & 0x3; | 307 | return (r >> 14) & 0x3; |
312 | } | 308 | } |
313 | static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_load_v(void) | 309 | static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_load_v(void) |
314 | { | 310 | { |
@@ -324,15 +320,15 @@ static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_switch_v(void) | |||
324 | } | 320 | } |
325 | static inline u32 fifo_intr_ctxsw_timeout_info_prev_tsgid_v(u32 r) | 321 | static inline u32 fifo_intr_ctxsw_timeout_info_prev_tsgid_v(u32 r) |
326 | { | 322 | { |
327 | return (r >> 4) & 0xfff; | 323 | return (r >> 0) & 0x3fff; |
328 | } | 324 | } |
329 | static inline u32 fifo_intr_ctxsw_timeout_info_next_tsgid_v(u32 r) | 325 | static inline u32 fifo_intr_ctxsw_timeout_info_next_tsgid_v(u32 r) |
330 | { | 326 | { |
331 | return (r >> 16) & 0xfff; | 327 | return (r >> 16) & 0x3fff; |
332 | } | 328 | } |
333 | static inline u32 fifo_intr_ctxsw_timeout_info_status_v(u32 r) | 329 | static inline u32 fifo_intr_ctxsw_timeout_info_status_v(u32 r) |
334 | { | 330 | { |
335 | return (r >> 28) & 0x3; | 331 | return (r >> 30) & 0x3; |
336 | } | 332 | } |
337 | static inline u32 fifo_intr_ctxsw_timeout_info_status_awaiting_ack_v(void) | 333 | static inline u32 fifo_intr_ctxsw_timeout_info_status_awaiting_ack_v(void) |
338 | { | 334 | { |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h index 965f8663..6c6dea4a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -78,6 +78,10 @@ static inline u32 pwr_falcon_irqstat_swgen0_true_f(void) | |||
78 | { | 78 | { |
79 | return 0x40; | 79 | return 0x40; |
80 | } | 80 | } |
81 | static inline u32 pwr_falcon_irqstat_ext_second_true_f(void) | ||
82 | { | ||
83 | return 0x800; | ||
84 | } | ||
81 | static inline u32 pwr_falcon_irqmode_r(void) | 85 | static inline u32 pwr_falcon_irqmode_r(void) |
82 | { | 86 | { |
83 | return 0x0010a00c; | 87 | return 0x0010a00c; |
@@ -118,6 +122,38 @@ static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v) | |||
118 | { | 122 | { |
119 | return (v & 0x1) << 7; | 123 | return (v & 0x1) << 7; |
120 | } | 124 | } |
125 | static inline u32 pwr_falcon_irqmset_ext_f(u32 v) | ||
126 | { | ||
127 | return (v & 0xff) << 8; | ||
128 | } | ||
129 | static inline u32 pwr_falcon_irqmset_ext_ctxe_f(u32 v) | ||
130 | { | ||
131 | return (v & 0x1) << 8; | ||
132 | } | ||
133 | static inline u32 pwr_falcon_irqmset_ext_limitv_f(u32 v) | ||
134 | { | ||
135 | return (v & 0x1) << 9; | ||
136 | } | ||
137 | static inline u32 pwr_falcon_irqmset_ext_second_f(u32 v) | ||
138 | { | ||
139 | return (v & 0x1) << 11; | ||
140 | } | ||
141 | static inline u32 pwr_falcon_irqmset_ext_therm_f(u32 v) | ||
142 | { | ||
143 | return (v & 0x1) << 12; | ||
144 | } | ||
145 | static inline u32 pwr_falcon_irqmset_ext_miscio_f(u32 v) | ||
146 | { | ||
147 | return (v & 0x1) << 13; | ||
148 | } | ||
149 | static inline u32 pwr_falcon_irqmset_ext_rttimer_f(u32 v) | ||
150 | { | ||
151 | return (v & 0x1) << 14; | ||
152 | } | ||
153 | static inline u32 pwr_falcon_irqmset_ext_rsvd8_f(u32 v) | ||
154 | { | ||
155 | return (v & 0x1) << 15; | ||
156 | } | ||
121 | static inline u32 pwr_falcon_irqmclr_r(void) | 157 | static inline u32 pwr_falcon_irqmclr_r(void) |
122 | { | 158 | { |
123 | return 0x0010a014; | 159 | return 0x0010a014; |
@@ -158,6 +194,34 @@ static inline u32 pwr_falcon_irqmclr_ext_f(u32 v) | |||
158 | { | 194 | { |
159 | return (v & 0xff) << 8; | 195 | return (v & 0xff) << 8; |
160 | } | 196 | } |
197 | static inline u32 pwr_falcon_irqmclr_ext_ctxe_f(u32 v) | ||
198 | { | ||
199 | return (v & 0x1) << 8; | ||
200 | } | ||
201 | static inline u32 pwr_falcon_irqmclr_ext_limitv_f(u32 v) | ||
202 | { | ||
203 | return (v & 0x1) << 9; | ||
204 | } | ||
205 | static inline u32 pwr_falcon_irqmclr_ext_second_f(u32 v) | ||
206 | { | ||
207 | return (v & 0x1) << 11; | ||
208 | } | ||
209 | static inline u32 pwr_falcon_irqmclr_ext_therm_f(u32 v) | ||
210 | { | ||
211 | return (v & 0x1) << 12; | ||
212 | } | ||
213 | static inline u32 pwr_falcon_irqmclr_ext_miscio_f(u32 v) | ||
214 | { | ||
215 | return (v & 0x1) << 13; | ||
216 | } | ||
217 | static inline u32 pwr_falcon_irqmclr_ext_rttimer_f(u32 v) | ||
218 | { | ||
219 | return (v & 0x1) << 14; | ||
220 | } | ||
221 | static inline u32 pwr_falcon_irqmclr_ext_rsvd8_f(u32 v) | ||
222 | { | ||
223 | return (v & 0x1) << 15; | ||
224 | } | ||
161 | static inline u32 pwr_falcon_irqmask_r(void) | 225 | static inline u32 pwr_falcon_irqmask_r(void) |
162 | { | 226 | { |
163 | return 0x0010a018; | 227 | return 0x0010a018; |
@@ -202,6 +266,34 @@ static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v) | |||
202 | { | 266 | { |
203 | return (v & 0xff) << 8; | 267 | return (v & 0xff) << 8; |
204 | } | 268 | } |
269 | static inline u32 pwr_falcon_irqdest_host_ext_ctxe_f(u32 v) | ||
270 | { | ||
271 | return (v & 0x1) << 8; | ||
272 | } | ||
273 | static inline u32 pwr_falcon_irqdest_host_ext_limitv_f(u32 v) | ||
274 | { | ||
275 | return (v & 0x1) << 9; | ||
276 | } | ||
277 | static inline u32 pwr_falcon_irqdest_host_ext_second_f(u32 v) | ||
278 | { | ||
279 | return (v & 0x1) << 11; | ||
280 | } | ||
281 | static inline u32 pwr_falcon_irqdest_host_ext_therm_f(u32 v) | ||
282 | { | ||
283 | return (v & 0x1) << 12; | ||
284 | } | ||
285 | static inline u32 pwr_falcon_irqdest_host_ext_miscio_f(u32 v) | ||
286 | { | ||
287 | return (v & 0x1) << 13; | ||
288 | } | ||
289 | static inline u32 pwr_falcon_irqdest_host_ext_rttimer_f(u32 v) | ||
290 | { | ||
291 | return (v & 0x1) << 14; | ||
292 | } | ||
293 | static inline u32 pwr_falcon_irqdest_host_ext_rsvd8_f(u32 v) | ||
294 | { | ||
295 | return (v & 0x1) << 15; | ||
296 | } | ||
205 | static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v) | 297 | static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v) |
206 | { | 298 | { |
207 | return (v & 0x1) << 16; | 299 | return (v & 0x1) << 16; |
@@ -238,6 +330,34 @@ static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v) | |||
238 | { | 330 | { |
239 | return (v & 0xff) << 24; | 331 | return (v & 0xff) << 24; |
240 | } | 332 | } |
333 | static inline u32 pwr_falcon_irqdest_target_ext_ctxe_f(u32 v) | ||
334 | { | ||
335 | return (v & 0x1) << 24; | ||
336 | } | ||
337 | static inline u32 pwr_falcon_irqdest_target_ext_limitv_f(u32 v) | ||
338 | { | ||
339 | return (v & 0x1) << 25; | ||
340 | } | ||
341 | static inline u32 pwr_falcon_irqdest_target_ext_second_f(u32 v) | ||
342 | { | ||
343 | return (v & 0x1) << 27; | ||
344 | } | ||
345 | static inline u32 pwr_falcon_irqdest_target_ext_therm_f(u32 v) | ||
346 | { | ||
347 | return (v & 0x1) << 28; | ||
348 | } | ||
349 | static inline u32 pwr_falcon_irqdest_target_ext_miscio_f(u32 v) | ||
350 | { | ||
351 | return (v & 0x1) << 29; | ||
352 | } | ||
353 | static inline u32 pwr_falcon_irqdest_target_ext_rttimer_f(u32 v) | ||
354 | { | ||
355 | return (v & 0x1) << 30; | ||
356 | } | ||
357 | static inline u32 pwr_falcon_irqdest_target_ext_rsvd8_f(u32 v) | ||
358 | { | ||
359 | return (v & 0x1) << 31; | ||
360 | } | ||
241 | static inline u32 pwr_falcon_curctx_r(void) | 361 | static inline u32 pwr_falcon_curctx_r(void) |
242 | { | 362 | { |
243 | return 0x0010a050; | 363 | return 0x0010a050; |