diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2018-02-13 06:12:12 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-03-13 17:09:24 -0400 |
commit | 663e941eb6382f60e3f468d645e256cb33c4e055 (patch) | |
tree | 60f717a4e61f608ddcb417e8aa01030219a68e3e /drivers/gpu/nvgpu/include | |
parent | a5364c30b1298aec1f2c9f89aee7d94a31619c19 (diff) |
gpu: nvgpu: PMU nv_pmu_boardobj & queue update
- Updated "struct nv_pmu_boardobj, nv_pmu_boardobj_query &
nv_pmu_boardobjgrp_super" by adding new members
as per gv10x PMU ucode boardobj interface.
- Created "PMU_QUEUE_COUNT_FOR_V5 4" for gv10x PMU ucode
- Created "PMU_QUEUE_MSG_IDX_FOR_V5 3" for gv10x PMU ucode
- Deleted unused "PMU_QUEUE_MSG_IDX_FOR_4"
- Updating "APP_VERSION_GV10X 23616379" for ucode
git CL: https://git-master.nvidia.com/r/#/c/1662993/
P4 CL#: 23647491
- Updating "APP_VERSION_GP10X 22099494" for ucode
git CL: https://git-master.nvidia.com/r/#/c/1662995/
P4 CL#: 23647537
Change-Id: I6e8e2b30e81422f8b529a2fad6d926f93bd73d3e
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1656643
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifboardobj.h | 6 |
2 files changed, 8 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h index 2dd511de..71684f6c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h | |||
@@ -107,12 +107,13 @@ struct pmu_init_msg_pmu_v1 { | |||
107 | u16 sw_managed_area_size; | 107 | u16 sw_managed_area_size; |
108 | }; | 108 | }; |
109 | 109 | ||
110 | #define PMU_QUEUE_COUNT_FOR_V5 4 | ||
110 | #define PMU_QUEUE_COUNT_FOR_V4 5 | 111 | #define PMU_QUEUE_COUNT_FOR_V4 5 |
111 | #define PMU_QUEUE_COUNT_FOR_V3 3 | 112 | #define PMU_QUEUE_COUNT_FOR_V3 3 |
112 | #define PMU_QUEUE_HPQ_IDX_FOR_V3 0 | 113 | #define PMU_QUEUE_HPQ_IDX_FOR_V3 0 |
113 | #define PMU_QUEUE_LPQ_IDX_FOR_V3 1 | 114 | #define PMU_QUEUE_LPQ_IDX_FOR_V3 1 |
114 | #define PMU_QUEUE_MSG_IDX_FOR_V3 2 | 115 | #define PMU_QUEUE_MSG_IDX_FOR_V3 2 |
115 | #define PMU_QUEUE_MSG_IDX_FOR_V4 4 | 116 | #define PMU_QUEUE_MSG_IDX_FOR_V5 3 |
116 | struct pmu_init_msg_pmu_v3 { | 117 | struct pmu_init_msg_pmu_v3 { |
117 | u8 msg_type; | 118 | u8 msg_type; |
118 | u8 queue_index[PMU_QUEUE_COUNT_FOR_V3]; | 119 | u8 queue_index[PMU_QUEUE_COUNT_FOR_V3]; |
@@ -144,8 +145,8 @@ struct pmu_init_msg_pmu_v4 { | |||
144 | struct pmu_init_msg_pmu_v5 { | 145 | struct pmu_init_msg_pmu_v5 { |
145 | u8 msg_type; | 146 | u8 msg_type; |
146 | u8 flcn_status; | 147 | u8 flcn_status; |
147 | u8 queue_index[PMU_QUEUE_COUNT_FOR_V4]; | 148 | u8 queue_index[PMU_QUEUE_COUNT_FOR_V5]; |
148 | u16 queue_size[PMU_QUEUE_COUNT_FOR_V4]; | 149 | u16 queue_size[PMU_QUEUE_COUNT_FOR_V5]; |
149 | u16 queue_offset; | 150 | u16 queue_offset; |
150 | 151 | ||
151 | u16 sw_managed_area_offset; | 152 | u16 sw_managed_area_offset; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifboardobj.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifboardobj.h index b8c1e394..697f95bc 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifboardobj.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifboardobj.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -43,6 +43,7 @@ | |||
43 | */ | 43 | */ |
44 | struct nv_pmu_boardobj { | 44 | struct nv_pmu_boardobj { |
45 | u8 type; | 45 | u8 type; |
46 | u8 grp_idx; | ||
46 | }; | 47 | }; |
47 | 48 | ||
48 | /* | 49 | /* |
@@ -51,6 +52,7 @@ struct nv_pmu_boardobj { | |||
51 | */ | 52 | */ |
52 | struct nv_pmu_boardobj_query { | 53 | struct nv_pmu_boardobj_query { |
53 | u8 type; | 54 | u8 type; |
55 | u8 grp_idx; | ||
54 | }; | 56 | }; |
55 | 57 | ||
56 | /* | 58 | /* |
@@ -61,7 +63,7 @@ struct nv_pmu_boardobjgrp_super { | |||
61 | u8 type; | 63 | u8 type; |
62 | u8 class_id; | 64 | u8 class_id; |
63 | u8 obj_slots; | 65 | u8 obj_slots; |
64 | u8 rsvd; | 66 | u8 flags; |
65 | }; | 67 | }; |
66 | 68 | ||
67 | struct nv_pmu_boardobjgrp { | 69 | struct nv_pmu_boardobjgrp { |