gpu: nvgpu: Update clk_vin interface as per chips_a

clk_vin data structures updated as new calibration type (v20) is added.
GP106 header does not have vin calibration type.
Assuming V10 if calibration type is not V20.
Add fuse calibration for V20 type.

Bug 200399373

Change-Id: I9449de1ecb0d0873f3bc16f46660f93fab5b9eac
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1687591
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2 files changed, 21 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/bios.h b/drivers/gpu/nvgpu/include/nvgpu/bios.h
index eec057f2..0619fcb9 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/bios.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/bios.h
@@ -137,6 +137,9 @@ struct vin_descriptor_entry_10 {
 #define NV_VIN_DESC_FLAGS0_VIN_CAL_REVISION_MASK 0x7
 #define NV_VIN_DESC_FLAGS0_VIN_CAL_REVISION_SHIFT 0
 
+#define NV_VIN_DESC_FLAGS0_VIN_CAL_TYPE_MASK 0xF0
+#define NV_VIN_DESC_FLAGS0_VIN_CAL_TYPE_SHIFT 4
+
 #define NV_VIN_DESC_FLAGS0_DISABLE_CONTROL_MASK 0x8
 #define NV_VIN_DESC_FLAGS0_DISABLE_CONTROL_SHIFT 3
 
@@ -152,6 +155,12 @@ struct vin_descriptor_entry_10 {
 #define NV_VIN_DESC_VIN_CAL_INTERCEPT_INTEGER_MASK 0xFFC0000
 #define NV_VIN_DESC_VIN_CAL_INTERCEPT_INTEGER_SHIFT 18
 
+#define NV_VIN_DESC_VIN_CAL_OFFSET_MASK 0x7F
+#define NV_VIN_DESC_VIN_CAL_OFFSET_SHIFT 0
+
+#define NV_VIN_DESC_VIN_CAL_GAIN_MASK 0xF80
+#define NV_VIN_DESC_VIN_CAL_GAIN_SHIFT 7
+
 #define VBIOS_CLOCKS_TABLE_1X_HEADER_SIZE_07 0x07
 struct vbios_clocks_table_1x_header {
         u8 version;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h
index 63bce913..e0a3313b 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h
@@ -251,14 +251,24 @@ struct nv_pmu_clk_clk_vin_device_boardobj_set {
         struct nv_pmu_boardobj super;
         u8 id;
         u8 volt_domain;
-        u32 slope;
-        u32 intercept;
         u32 flls_shared_mask;
 };
 
+struct nv_pmu_clk_clk_vin_device_v10_boardobj_set {
+        struct nv_pmu_clk_clk_vin_device_boardobj_set super;
+        struct ctrl_clk_vin_device_info_data_v10 data;
+};
+
+struct nv_pmu_clk_clk_vin_device_v20_boardobj_set {
+        struct nv_pmu_clk_clk_vin_device_boardobj_set super;
+        struct ctrl_clk_vin_device_info_data_v20 data;
+};
+
 union nv_pmu_clk_clk_vin_device_boardobj_set_union {
         struct nv_pmu_boardobj board_obj;
         struct nv_pmu_clk_clk_vin_device_boardobj_set super;
+        struct nv_pmu_clk_clk_vin_device_v10_boardobj_set v10;
+        struct nv_pmu_clk_clk_vin_device_v20_boardobj_set v20;
 };
 
 NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_vin_device);