diff options
author | Aparna Das <aparnad@nvidia.com> | 2020-01-31 15:34:07 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2020-02-05 06:25:01 -0500 |
commit | 63e9d8eb9ad80724f2567aaa7c05cb2c7acfd4b1 (patch) | |
tree | a66df8619d3faa42f1f8d106a401fc34824953ad /drivers/gpu/nvgpu/include | |
parent | e41fd090315ff37fa09314a8cfde6d384385e17a (diff) |
gpu: nvgpu: vgpu: add mmu_debug_mode support
Added two new IVC commands that set gr and fb mmu debug mode.
Bug 2586624
Change-Id: I358fb04713a9754fb209c0a90d02130dd4a1caf6
Reviewed-on: https://git-master.nvidia.com/r/2204980
(cherry picked from commit db4e5b09891aff075dfffb7cc2fe0630a71ab9a6)
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2288347
Reviewed-by: Kajetan Dutka <kdutka@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Kajetan Dutka <kdutka@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h | 13 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/vgpu/vgpu.h | 5 |
2 files changed, 17 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h index 6abb5e33..e33dce94 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h | |||
@@ -123,6 +123,8 @@ enum { | |||
123 | TEGRA_VGPU_CMD_RESUME = 83, | 123 | TEGRA_VGPU_CMD_RESUME = 83, |
124 | TEGRA_VGPU_CMD_GET_ECC_INFO = 84, | 124 | TEGRA_VGPU_CMD_GET_ECC_INFO = 84, |
125 | TEGRA_VGPU_CMD_GET_ECC_COUNTER_VALUE = 85, | 125 | TEGRA_VGPU_CMD_GET_ECC_COUNTER_VALUE = 85, |
126 | TEGRA_VGPU_CMD_FB_SET_MMU_DEBUG_MODE = 88, | ||
127 | TEGRA_VGPU_CMD_GR_SET_MMU_DEBUG_MODE = 89, | ||
126 | }; | 128 | }; |
127 | 129 | ||
128 | struct tegra_vgpu_connect_params { | 130 | struct tegra_vgpu_connect_params { |
@@ -617,6 +619,15 @@ struct tegra_vgpu_tsg_bind_channel_ex_params { | |||
617 | u32 runqueue_sel; | 619 | u32 runqueue_sel; |
618 | }; | 620 | }; |
619 | 621 | ||
622 | struct tegra_vgpu_fb_set_mmu_debug_mode_params { | ||
623 | u8 enable; | ||
624 | }; | ||
625 | |||
626 | struct tegra_vgpu_gr_set_mmu_debug_mode_params { | ||
627 | u64 ch_handle; | ||
628 | u8 enable; | ||
629 | }; | ||
630 | |||
620 | struct tegra_vgpu_cmd_msg { | 631 | struct tegra_vgpu_cmd_msg { |
621 | u32 cmd; | 632 | u32 cmd; |
622 | int ret; | 633 | int ret; |
@@ -679,6 +690,8 @@ struct tegra_vgpu_cmd_msg { | |||
679 | struct tegra_vgpu_channel_update_pc_sampling update_pc_sampling; | 690 | struct tegra_vgpu_channel_update_pc_sampling update_pc_sampling; |
680 | struct tegra_vgpu_ecc_info_params ecc_info; | 691 | struct tegra_vgpu_ecc_info_params ecc_info; |
681 | struct tegra_vgpu_ecc_counter_params ecc_counter; | 692 | struct tegra_vgpu_ecc_counter_params ecc_counter; |
693 | struct tegra_vgpu_fb_set_mmu_debug_mode_params fb_set_mmu_debug_mode; | ||
694 | struct tegra_vgpu_gr_set_mmu_debug_mode_params gr_set_mmu_debug_mode; | ||
682 | char padding[192]; | 695 | char padding[192]; |
683 | } params; | 696 | } params; |
684 | }; | 697 | }; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/vgpu/vgpu.h b/drivers/gpu/nvgpu/include/nvgpu/vgpu/vgpu.h index 15ab879e..ecdb8964 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/vgpu/vgpu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/vgpu/vgpu.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -39,6 +39,7 @@ struct vm_gk20a; | |||
39 | struct nvgpu_gr_ctx; | 39 | struct nvgpu_gr_ctx; |
40 | struct nvgpu_cpu_time_correlation_sample; | 40 | struct nvgpu_cpu_time_correlation_sample; |
41 | struct vgpu_ecc_stat; | 41 | struct vgpu_ecc_stat; |
42 | struct channel_gk20a; | ||
42 | 43 | ||
43 | struct vgpu_priv_data { | 44 | struct vgpu_priv_data { |
44 | u64 virt_handle; | 45 | u64 virt_handle; |
@@ -104,4 +105,6 @@ int vgpu_gv11b_init_hal(struct gk20a *g); | |||
104 | 105 | ||
105 | bool vgpu_is_reduced_bar1(struct gk20a *g); | 106 | bool vgpu_is_reduced_bar1(struct gk20a *g); |
106 | 107 | ||
108 | int vgpu_gr_set_mmu_debug_mode(struct gk20a *g, | ||
109 | struct channel_gk20a *ch, bool enable); | ||
107 | #endif | 110 | #endif |