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authorMahantesh Kumbar <mkumbar@nvidia.com>2018-09-23 04:56:26 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-09-27 11:33:34 -0400
commit628e2c79017b83032a840fb85e136d3216dec9c4 (patch)
tree2b8c3c75698d96a9e5e6ee1519ff8dbfb6cccdd2 /drivers/gpu/nvgpu/include
parent850f2ad8ada4f4c2c753644f387d75e6d75ac28b (diff)
gpu: nvgpu: falcon engine EMEM support
-Added HAL copy_from_emem & copy_to_emem to struct nvgpu_falcon_engine_dependency_ops data struct to point to engine specific EMEM access functions. -Added function nvgpu_flcn_copy_from_emem() & nvgpu_flcn_copy_to_emem() at interface layer to access EMEM using flacon engine EMEM HAL's. JIRA NVGPU-1161 Change-Id: Ifb72a617277e73f25f1772c969791b642585e7fb Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1807336 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/falcon.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/falcon.h b/drivers/gpu/nvgpu/include/nvgpu/falcon.h
index 9f8c97ea..cf15061d 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/falcon.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/falcon.h
@@ -219,6 +219,10 @@ struct nvgpu_falcon_engine_dependency_ops {
219 int (*queue_tail)(struct gk20a *g, struct nvgpu_falcon_queue *queue, 219 int (*queue_tail)(struct gk20a *g, struct nvgpu_falcon_queue *queue,
220 u32 *tail, bool set); 220 u32 *tail, bool set);
221 void (*msgq_tail)(struct gk20a *g, u32 *tail, bool set); 221 void (*msgq_tail)(struct gk20a *g, u32 *tail, bool set);
222 int (*copy_from_emem)(struct nvgpu_falcon *flcn, u32 src, u8 *dst,
223 u32 size, u8 port);
224 int (*copy_to_emem)(struct nvgpu_falcon *flcn, u32 dst, u8 *src,
225 u32 size, u8 port);
222}; 226};
223 227
224struct nvgpu_falcon_ops { 228struct nvgpu_falcon_ops {
@@ -283,6 +287,10 @@ bool nvgpu_flcn_get_mem_scrubbing_status(struct nvgpu_falcon *flcn);
283int nvgpu_flcn_mem_scrub_wait(struct nvgpu_falcon *flcn); 287int nvgpu_flcn_mem_scrub_wait(struct nvgpu_falcon *flcn);
284bool nvgpu_flcn_get_cpu_halted_status(struct nvgpu_falcon *flcn); 288bool nvgpu_flcn_get_cpu_halted_status(struct nvgpu_falcon *flcn);
285bool nvgpu_flcn_get_idle_status(struct nvgpu_falcon *flcn); 289bool nvgpu_flcn_get_idle_status(struct nvgpu_falcon *flcn);
290int nvgpu_flcn_copy_from_emem(struct nvgpu_falcon *flcn,
291 u32 src, u8 *dst, u32 size, u8 port);
292int nvgpu_flcn_copy_to_emem(struct nvgpu_falcon *flcn,
293 u32 dst, u8 *src, u32 size, u8 port);
286int nvgpu_flcn_copy_from_dmem(struct nvgpu_falcon *flcn, 294int nvgpu_flcn_copy_from_dmem(struct nvgpu_falcon *flcn,
287 u32 src, u8 *dst, u32 size, u8 port); 295 u32 src, u8 *dst, u32 size, u8 port);
288int nvgpu_flcn_copy_to_dmem(struct nvgpu_falcon *flcn, 296int nvgpu_flcn_copy_to_dmem(struct nvgpu_falcon *flcn,