gpu: nvgpu: ACR code refactor

-Created struct nvgpu_acr to hold acr module related member
 within single struct which are currently spread across multiple structs
 like nvgpu_pmu, pmu_ops & gk20a.
-Created struct hs_flcn_bl struct to hold ACR HS bootloader specific members
-Created struct hs_acr to hold ACR ucode specific members like bootloader data
 using struct hs_flcn_bl, acr type & falcon info on which ACR ucode need to run.
-Created acr ops under struct nvgpu_acr	to perform ACR specific operation,
 currently ACR ops were part PMU which caused to have always dependence
 on PMU even though ACR was not executing on PMU.
-Added acr_remove_support ops which will be called as part of
 gk20a_remove_support() method, earlier acr cleanup was part of
 pmu remove_support method.
-Created define for ACR types,
-Ops acr_sw_init() function helps to set ACR properties
 statically for chip currently in execution & assign ops to point to
 needed functions as per chip.
-Ops acr_sw_init execute at early as nvgpu_init_mm_support calls acr
 function to alloc blob space.
-Created ops to fill bootloader descriptor & to patch WPR info to ACR uocde
 based on interfaces used to bootstrap ACR ucode.
-Created function gm20b_bootstrap_hs_acr() function which is now common
 HAL for all chips to bootstrap ACR, earlier had 3 different function for
 gm20b/gp10b, gv11b & for all dgpu based on interface needed.
-Removed duplicate code for falcon engine wherever common falcon code can be used.
-Removed ACR code dependent on PMU & made changes to use from nvgpu_acr.

JIRA NVGPU-1148

Change-Id: I39951d2fc9a0bb7ee6057e0fa06da78045d47590
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1813231
GVS: Gerrit_Virtual_Submit
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2 files changed, 95 insertions, 22 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h b/drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h
index a9ed6e68..5fb26e1a 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -23,6 +23,8 @@
 #ifndef __NVGPU_ACR_H__
 #define __NVGPU_ACR_H__
 
+#include <nvgpu/falcon.h>
+
 #include "gk20a/mm_gk20a.h"
 
 #include "acr_lsfm.h"
@@ -31,6 +33,13 @@
 #include "acr_objflcn.h"
 
 struct nvgpu_firmware;
+struct gk20a;
+struct hs_acr_ops;
+struct hs_acr;
+struct nvgpu_acr;
+
+#define HSBIN_ACR_BL_UCODE_IMAGE "pmu_bl.bin"
+#define HSBIN_ACR_UCODE_IMAGE "acr_ucode.bin"
 
 #define MAX_SUPPORTED_LSFM 3 /*PMU, FECS, GPCCS*/
 
@@ -77,29 +86,94 @@ struct wpr_carveout_info {
         u64 size;
 };
 
-struct acr_desc {
-        struct nvgpu_mem ucode_blob;
-        struct nvgpu_mem wpr_dummy;
-        struct bin_hdr *bl_bin_hdr;
-        struct hsflcn_bl_desc *pmu_hsbl_desc;
-        struct bin_hdr *hsbin_hdr;
-        struct acr_fw_header *fw_hdr;
-        u32 pmu_args;
+/* ACR interfaces */
+
+struct hs_flcn_bl {
+        char *bl_fw_name;
+        struct nvgpu_firmware *hs_bl_fw;
+        struct hsflcn_bl_desc *hs_bl_desc;
+        struct bin_hdr *hs_bl_bin_hdr;
+        struct nvgpu_mem hs_bl_ucode;
+};
+
+struct hs_acr {
+        u32 acr_type;
+
+        /* HS bootloader to validate & load ACR ucode */
+        struct hs_flcn_bl acr_hs_bl;
+
+        /* ACR ucode */
+        char *acr_fw_name;
         struct nvgpu_firmware *acr_fw;
-        union{
-                struct flcn_acr_desc *acr_dmem_desc;
-                struct flcn_acr_desc_v1 *acr_dmem_desc_v1;
-        };
         struct nvgpu_mem acr_ucode;
-        struct nvgpu_firmware *hsbl_fw;
-        struct nvgpu_mem hsbl_ucode;
+
         union {
                 struct flcn_bl_dmem_desc bl_dmem_desc;
                 struct flcn_bl_dmem_desc_v1 bl_dmem_desc_v1;
         };
+
+        void *ptr_bl_dmem_desc;
+        u32 bl_dmem_desc_size;
+
+        union{
+                struct flcn_acr_desc *acr_dmem_desc;
+                struct flcn_acr_desc_v1 *acr_dmem_desc_v1;
+        };
+
+        /* Falcon used to execute ACR ucode */
+        struct nvgpu_falcon *acr_flcn;
+
+        int (*acr_flcn_setup_hw_and_bl_bootstrap)(struct gk20a *g,
+                struct hs_acr *acr_desc,
+                struct nvgpu_falcon_bl_info *bl_info);
+};
+
+#define ACR_DEFAULT     0U
+#define ACR_AHESASC     1U
+#define ACR_ASB         2U
+
+struct nvgpu_acr {
+        struct gk20a *g;
+
+        u32 bootstrap_owner;
+        u32 max_supported_lsfm;
+        u32 capabilities;
+
+        /*
+         * non-wpr space to hold LSF ucodes,
+         * ACR does copy ucode from non-wpr to wpr
+         */
+        struct nvgpu_mem ucode_blob;
+        /*
+         * Even though this mem_desc wouldn't be used,
+         * the wpr region needs to be reserved in the
+         * allocator in dGPU case.
+         */
+        struct nvgpu_mem wpr_dummy;
+
+        /* ACR member for different types of ucode */
+        /* For older dgpu/tegra ACR cuode */
+        struct hs_acr acr;
+        /* ACR load split feature support */
+        struct hs_acr acr_ahesasc;
+        struct hs_acr acr_asb;
+
+        u32 pmu_args;
         struct nvgpu_firmware *pmu_fw;
         struct nvgpu_firmware *pmu_desc;
-        u32 capabilities;
-};
 
+        int (*prepare_ucode_blob)(struct gk20a *g, struct nvgpu_acr *acr);
+        void (*get_wpr_info)(struct gk20a *g, struct wpr_carveout_info *inf);
+        int (*alloc_blob_space)(struct gk20a *g, size_t size,
+                struct nvgpu_mem *mem);
+        int (*patch_wpr_info_to_ucode)(struct gk20a *g, struct nvgpu_acr *acr,
+                struct hs_acr *acr_desc, bool is_recovery);
+        int (*acr_fill_bl_dmem_desc)(struct gk20a *g,
+                struct nvgpu_acr *acr, struct hs_acr *acr_desc,
+                u32 *acr_ucode_header);
+        int (*bootstrap_hs_acr)(struct gk20a *g, struct nvgpu_acr *acr,
+                struct hs_acr *acr_desc);
+
+        void (*remove_support)(struct nvgpu_acr *acr);
+};
 #endif /*__NVGPU_ACR_H__*/
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
index 6f57fddc..892aa9af 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
@@ -1054,9 +1054,6 @@ struct gpu_ops {
                 bool (*is_engine_in_reset)(struct gk20a *g);
                 bool (*is_lazy_bootstrap)(u32 falcon_id);
                 bool (*is_priv_load)(u32 falcon_id);
-                void (*get_wpr)(struct gk20a *g, struct wpr_carveout_info *inf);
-                int (*alloc_blob_space)(struct gk20a *g,
-                                size_t size, struct nvgpu_mem *mem);
                 int (*pmu_populate_loader_cfg)(struct gk20a *g,
                         void *lsfm,     u32 *p_bl_gen_desc_size);
                 int (*flcn_populate_bl_dmem_desc)(struct gk20a *g,
@@ -1318,6 +1315,9 @@ struct gpu_ops {
                 u32 (*get_nvhsclk_ctrl_swap_clk_nvl)(struct gk20a *g);
                 void (*set_nvhsclk_ctrl_swap_clk_nvl)(struct gk20a *g, u32 val);
         } top;
+        struct {
+                void (*acr_sw_init)(struct gk20a *g, struct nvgpu_acr *acr);
+        } acr;
         void (*semaphore_wakeup)(struct gk20a *g, bool post_events);
 };
 
@@ -1429,7 +1429,7 @@ struct gk20a {
         struct sim_nvgpu *sim;
         struct mm_gk20a mm;
         struct nvgpu_pmu pmu;
-        struct acr_desc acr;
+        struct nvgpu_acr acr;
         struct nvgpu_ecc ecc;
         struct clk_pmupstate clk_pmu;
         struct perf_pmupstate perf_pmu;
@@ -1477,7 +1477,6 @@ struct gk20a {
         u32 disable_syncpoints;
 
         bool support_pmu;
-        u32 bootstrap_owner;
 
         bool is_virtual;