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authorAlex Waterman <alexw@nvidia.com>2018-02-28 12:19:19 -0500
committerSrikar Srimath Tirumala <srikars@nvidia.com>2018-02-28 16:49:22 -0500
commit5a35a95654d561fce09a3b9abf6b82bb7a29d74b (patch)
tree119a07134188d8e06c29a570dd8c6b143f39c9e1 /drivers/gpu/nvgpu/include
parent3fdd8e38b280123fd13bcc4f3fd8928c15e94db6 (diff)
Revert "gpu: nvgpu: Get coherency on gv100 + NVLINK working"
Also revert other changes related to IO coherence. This may be the culprit in a recent dev-kernel lockdown. Bug 2070609 Change-Id: Ida178aef161fadbc6db9512521ea51c702c1564b Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1665914 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Srikar Srimath Tirumala <srikars@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/enabled.h4
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h23
2 files changed, 8 insertions, 19 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/enabled.h b/drivers/gpu/nvgpu/include/nvgpu/enabled.h
index 24748a19..a3d9df24 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/enabled.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/enabled.h
@@ -75,8 +75,8 @@ struct gk20a;
75#define NVGPU_SUPPORT_MAP_DIRECT_KIND_CTRL 24 75#define NVGPU_SUPPORT_MAP_DIRECT_KIND_CTRL 24
76/* Support batch mapping */ 76/* Support batch mapping */
77#define NVGPU_SUPPORT_MAP_BUFFER_BATCH 25 77#define NVGPU_SUPPORT_MAP_BUFFER_BATCH 25
78/* Use coherent aperture for sysmem. */ 78/* Support DMA coherence */
79#define NVGPU_USE_COHERENT_SYSMEM 26 79#define NVGPU_DMA_COHERENT 26
80/* Use physical scatter tables instead of IOMMU */ 80/* Use physical scatter tables instead of IOMMU */
81#define NVGPU_MM_USE_PHYSICAL_SG 27 81#define NVGPU_MM_USE_PHYSICAL_SG 27
82 82
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h
index f1ab8a6e..2b8b7015 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h
@@ -25,7 +25,6 @@
25 25
26#include <nvgpu/types.h> 26#include <nvgpu/types.h>
27#include <nvgpu/list.h> 27#include <nvgpu/list.h>
28#include <nvgpu/enabled.h>
29 28
30#ifdef __KERNEL__ 29#ifdef __KERNEL__
31#include <nvgpu/linux/nvgpu_mem.h> 30#include <nvgpu/linux/nvgpu_mem.h>
@@ -52,10 +51,6 @@ struct nvgpu_page_alloc;
52enum nvgpu_aperture { 51enum nvgpu_aperture {
53 APERTURE_INVALID = 0, /* unallocated or N/A */ 52 APERTURE_INVALID = 0, /* unallocated or N/A */
54 APERTURE_SYSMEM, 53 APERTURE_SYSMEM,
55
56 /* Don't use directly. Use APERTURE_SYSMEM, this is used internally. */
57 __APERTURE_SYSMEM_COH,
58
59 APERTURE_VIDMEM 54 APERTURE_VIDMEM
60}; 55};
61 56
@@ -192,18 +187,12 @@ nvgpu_mem_from_clear_list_entry(struct nvgpu_list_node *node)
192 clear_list_entry)); 187 clear_list_entry));
193}; 188};
194 189
195static inline const char *nvgpu_aperture_str(struct gk20a *g, 190static inline const char *nvgpu_aperture_str(enum nvgpu_aperture aperture)
196 enum nvgpu_aperture aperture)
197{ 191{
198 switch (aperture) { 192 switch (aperture) {
199 case APERTURE_INVALID: 193 case APERTURE_INVALID: return "INVAL";
200 return "INVAL"; 194 case APERTURE_SYSMEM: return "SYSMEM";
201 case APERTURE_SYSMEM: 195 case APERTURE_VIDMEM: return "VIDMEM";
202 return "SYSMEM";
203 case __APERTURE_SYSMEM_COH:
204 return "SYSCOH";
205 case APERTURE_VIDMEM:
206 return "VIDMEM";
207 }; 196 };
208 return "UNKNOWN"; 197 return "UNKNOWN";
209} 198}
@@ -333,9 +322,9 @@ u64 nvgpu_mem_get_addr(struct gk20a *g, struct nvgpu_mem *mem);
333u64 nvgpu_mem_get_phys_addr(struct gk20a *g, struct nvgpu_mem *mem); 322u64 nvgpu_mem_get_phys_addr(struct gk20a *g, struct nvgpu_mem *mem);
334 323
335u32 __nvgpu_aperture_mask(struct gk20a *g, enum nvgpu_aperture aperture, 324u32 __nvgpu_aperture_mask(struct gk20a *g, enum nvgpu_aperture aperture,
336 u32 sysmem_mask, u32 sysmem_coh_mask, u32 vidmem_mask); 325 u32 sysmem_mask, u32 vidmem_mask);
337u32 nvgpu_aperture_mask(struct gk20a *g, struct nvgpu_mem *mem, 326u32 nvgpu_aperture_mask(struct gk20a *g, struct nvgpu_mem *mem,
338 u32 sysmem_mask, u32 sysmem_coh_mask, u32 vidmem_mask); 327 u32 sysmem_mask, u32 vidmem_mask);
339 328
340u64 nvgpu_mem_iommu_translate(struct gk20a *g, u64 phys); 329u64 nvgpu_mem_iommu_translate(struct gk20a *g, u64 phys);
341 330