gpu: nvgpu: Update vfe_var interface as per chips_a_23609936

Changes made:
1. Fuse value can now be signed or unsigned. A new boolean added to check
if the value is signed or not.
2. Masks added for dependent variable and equations
3. Restructing some data structures as per r384

JIRA NVGPUGV100-39

Change-Id: I7d9d1a55e26a06686f6253dedeb55925a32fd0ad
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1597761
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaikundanathan S <vaikuns@nvidia.com>
Tested-by: Vaikundanathan S <vaikuns@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2 files changed, 14 insertions, 34 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/bios.h b/drivers/gpu/nvgpu/include/nvgpu/bios.h
index 191f0dbd..eec057f2 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/bios.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/bios.h
@@ -321,6 +321,9 @@ struct vbios_vfe_3x_var_entry_struct {
 #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_MASK 0x1000000
 #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_SHIFT 24
 
+#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VALUE_SIGNED_INTEGER_MASK 0x2000000
+#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VALUE_SIGNED_INTEGER_SHIFT 25
+
 #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_YES 0x00000001
 #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_NO 0x00000000
 #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_0_MASK 0xFF
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperfvfe.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperfvfe.h
index 18568a4d..7764c72a 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperfvfe.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperfvfe.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -24,11 +24,11 @@
 
 #include "gpmuifbios.h"
 #include "gpmuifboardobj.h"
+#include "ctrl/ctrlperf.h"
 
 #define CTRL_PERF_VFE_EQU_QUADRATIC_COEFF_COUNT                      0x03
 #define NV_PMU_PERF_RPC_VFE_EQU_EVAL_VAR_COUNT_MAX                             2
 #define NV_PMU_PERF_RPC_VFE_EQU_MONITOR_COUNT_MAX                             16
-#define NV_PMU_VFE_VAR_SINGLE_SENSED_FUSE_SEGMENTS_MAX                        1
 
 struct nv_pmu_perf_vfe_var_value {
         u8 var_type;
@@ -66,8 +66,8 @@ struct nv_pmu_perf_vfe_var_get_status_super {
 
 struct nv_pmu_perf_vfe_var_single_sensed_fuse_get_status {
         struct nv_pmu_perf_vfe_var_get_status_super super;
-        u32 fuse_value_integer;
-        u32 fuse_value_hw_integer;
+        struct ctrl_perf_vfe_var_single_sensed_fuse_value fuse_value_integer;
+        struct ctrl_perf_vfe_var_single_sensed_fuse_value fuse_value_hw_integer;
         u8 fuse_version;
         bool b_version_check_failed;
 };
@@ -84,6 +84,8 @@ struct nv_pmu_vfe_var {
         struct nv_pmu_boardobj super;
         u32 out_range_min;
         u32 out_range_max;
+        struct ctrl_boardobjgrp_mask_e32 mask_dependent_vars;
+        struct ctrl_boardobjgrp_mask_e255 mask_dependent_equs;
 };
 
 struct nv_pmu_vfe_var_derived {
@@ -116,38 +118,13 @@ struct nv_pmu_vfe_var_single_sensed {
         struct nv_pmu_vfe_var_single super;
 };
 
-struct nv_pmu_vfe_var_single_sensed_fuse_info {
-        u8 segment_count;
-        union nv_pmu_bios_vfield_register_segment segments[
-                NV_PMU_VFE_VAR_SINGLE_SENSED_FUSE_SEGMENTS_MAX];
-};
-
-struct nv_pmu_vfe_var_single_sensed_fuse_vfield_info {
-        struct nv_pmu_vfe_var_single_sensed_fuse_info fuse;
-        u32 fuse_val_default;
-        int hw_correction_scale;
-        int hw_correction_offset;
-        u8 v_field_id;
-};
-
-struct nv_pmu_vfe_var_single_sensed_fuse_ver_vfield_info {
-        struct nv_pmu_vfe_var_single_sensed_fuse_info fuse;
-        u8 ver_expected;
-        bool b_ver_check;
-        bool b_use_default_on_ver_check_fail;
-        u8 v_field_id_ver;
-};
-
-struct nv_pmu_vfe_var_single_sensed_fuse_override_info {
-        u32 fuse_val_override;
-        bool b_fuse_regkey_override;
-};
-
 struct nv_pmu_vfe_var_single_sensed_fuse {
         struct nv_pmu_vfe_var_single_sensed super;
-        struct nv_pmu_vfe_var_single_sensed_fuse_override_info override_info;
-        struct nv_pmu_vfe_var_single_sensed_fuse_vfield_info vfield_info;
-        struct nv_pmu_vfe_var_single_sensed_fuse_ver_vfield_info vfield_ver_info;
+        struct ctrl_perf_vfe_var_single_sensed_fuse_override_info override_info;
+        struct ctrl_perf_vfe_var_single_sensed_fuse_vfield_info vfield_info;
+        struct ctrl_perf_vfe_var_single_sensed_fuse_ver_vfield_info vfield_ver_info;
+        struct ctrl_perf_vfe_var_single_sensed_fuse_value fuse_val_default;
+        bool b_fuse_value_signed;
 };
 
 struct nv_pmu_vfe_var_single_sensed_temp {