gpu: nvgpu: Generalize BIOS code

Most of BIOS parsing code is not specific to any particular GPU. Move
most of the code to generic files, and leave only chip specific parts
dealing with microcontroller boot into chip specific files.

As most of the parsing is generic, they do not need to be called via
HALs so remove the HALs and change the calls into direct function
calls.

All definitions meant to be used outside BIOS code itself are now in
<nvgpu/bios.h>

Change-Id: Id48e94c74511d6e95645e90e5bba5c12ef8da45d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1302222
GVS: Gerrit_Virtual_Submit

1 files changed, 60 insertions, 6 deletions

diff --git a/drivers/gpu/nvgpu/include/bios.h b/drivers/gpu/nvgpu/include/nvgpu/bios.h
index bcb24343..c6465313 100644
--- a/drivers/gpu/nvgpu/include/bios.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/bios.h
@@ -1,7 +1,5 @@
 /*
- * vbios tables support
- *
- * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -13,10 +11,58 @@
  * more details.
  */
 
-#ifndef NVGPU_INCLUDE_BIOS_H
-#define NVGPU_INCLUDE_BIOS_H
+#ifndef NVGPU_BIOS_H
+#define NVGPU_BIOS_H
+
+#include <linux/types.h>
+
+struct gk20a;
+
+#define PERF_PTRS_WIDTH 0x4
+#define PERF_PTRS_WIDTH_16 0x2
+
+enum {
+        CLOCKS_TABLE = 2,
+        CLOCK_PROGRAMMING_TABLE,
+        FLL_TABLE,
+        VIN_TABLE,
+        FREQUENCY_CONTROLLER_TABLE
+};
 
-#include "gk20a/gk20a.h"
+enum {
+        PERFORMANCE_TABLE = 0,
+        MEMORY_CLOCK_TABLE,
+        MEMORY_TWEAK_TABLE,
+        POWER_CONTROL_TABLE,
+        THERMAL_CONTROL_TABLE,
+        THERMAL_DEVICE_TABLE,
+        THERMAL_COOLERS_TABLE,
+        PERFORMANCE_SETTINGS_SCRIPT,
+        CONTINUOUS_VIRTUAL_BINNING_TABLE,
+        POWER_SENSORS_TABLE = 0xA,
+        POWER_CAPPING_TABLE = 0xB,
+        POWER_TOPOLOGY_TABLE = 0xF,
+        THERMAL_CHANNEL_TABLE = 0x12,
+        VOLTAGE_RAIL_TABLE = 26,
+        VOLTAGE_DEVICE_TABLE,
+        VOLTAGE_POLICY_TABLE,
+        LOWPOWER_TABLE,
+        LOWPOWER_GR_TABLE = 32,
+        LOWPOWER_MS_TABLE = 33,
+};
+
+enum {
+        VP_FIELD_TABLE = 0,
+        VP_FIELD_REGISTER,
+        VP_TRANSLATION_TABLE,
+};
+
+struct bit_token {
+        u8 token_id;
+        u8 data_version;
+        u16 data_size;
+        u16 data_ptr;
+} __packed;
 
 #define BIOS_GET_FIELD(value, name) ((value & name##_MASK) >> name##_SHIFT)
 
@@ -988,5 +1034,13 @@ struct nvgpu_bios_lpwr_gr_table_1x_entry {
 
 #define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_RPPG_MASK GENMASK(4, 4)
 #define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_RPPG_SHIFT 4
+int nvgpu_bios_parse_rom(struct gk20a *g);
+u8 nvgpu_bios_read_u8(struct gk20a *g, u32 offset);
+s8 nvgpu_bios_read_s8(struct gk20a *g, u32 offset);
+u16 nvgpu_bios_read_u16(struct gk20a *g, u32 offset);
+u32 nvgpu_bios_read_u32(struct gk20a *g, u32 offset);
+void *nvgpu_bios_get_perf_table_ptrs(struct gk20a *g,
+                struct bit_token *ptoken, u8 table_id);
+int nvgpu_bios_execute_script(struct gk20a *g, u32 offset);
 
 #endif