gpu: nvgpu: ACR load split feature support

-Added code to copy SEC2-RTOS ucode to non-wpr blob
  as part of prepare ucode blob.
-Added code to setup & bootstrap GSP, as ACR-ASB needs
 ucode to execute on GSP falcon.
-Defined LSF_FALCON_ID_GSPLITE for GSP falcon
-Defined HSBIN_ACR_AHESASC_DBG/PROD_UCODE &
 HSBIN_ACR_ASB_DBG/PROD_UCODE to hold names
 of ACR AHESASC/ASB ucodes.
-Added defines to hold name of SE2C RTOS ucodes

JIRA NVGPUT-134

Change-Id: I824afed41f785a4ca0fb393bd023db5396c7a399
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1790179
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

3 files changed, 37 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h b/drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h
index 90d2d20d..f9d9e2a8 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h
@@ -48,7 +48,7 @@
  * Defines a common Light Secure Falcon identifier.
  */
 #define LSF_FALCON_ID_PMU       (0)
-#define LSF_FALCON_ID_RESERVED  (1)
+#define LSF_FALCON_ID_GSPLITE   (1)
 #define LSF_FALCON_ID_FECS      (2)
 #define LSF_FALCON_ID_GPCCS     (3)
 #define LSF_FALCON_ID_SEC2      (7)
diff --git a/drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h b/drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h
index 5fb26e1a..ba658c95 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h
@@ -40,6 +40,14 @@ struct nvgpu_acr;
 
 #define HSBIN_ACR_BL_UCODE_IMAGE "pmu_bl.bin"
 #define HSBIN_ACR_UCODE_IMAGE "acr_ucode.bin"
+#define HSBIN_ACR_AHESASC_PROD_UCODE "acr_ahesasc_prod_ucode.bin"
+#define HSBIN_ACR_ASB_PROD_UCODE "acr_asb_prod_ucode.bin"
+#define HSBIN_ACR_AHESASC_DBG_UCODE "acr_ahesasc_dbg_ucode.bin"
+#define HSBIN_ACR_ASB_DBG_UCODE "acr_asb_dbg_ucode.bin"
+
+#define LSF_SEC2_UCODE_IMAGE_BIN "sec2_ucode_image.bin"
+#define LSF_SEC2_UCODE_DESC_BIN "sec2_ucode_desc.bin"
+#define LSF_SEC2_UCODE_SIG_BIN "sec2_sig.bin"
 
 #define MAX_SUPPORTED_LSFM 3 /*PMU, FECS, GPCCS*/
 
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pgsp_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pgsp_gv100.h
index f0f5bc26..34d0eae8 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pgsp_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pgsp_gv100.h
@@ -252,6 +252,26 @@ static inline u32 pgsp_falcon_nxtctx_r(void)
 {
         return 0x00110054U;
 }
+static inline u32 pgsp_falcon_nxtctx_ctxptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 pgsp_falcon_nxtctx_ctxtgt_fb_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pgsp_falcon_nxtctx_ctxtgt_sys_coh_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 pgsp_falcon_nxtctx_ctxtgt_sys_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 pgsp_falcon_nxtctx_ctxvalid_f(u32 v)
+{
+        return (v & 0x1U) << 30U;
+}
 static inline u32 pgsp_falcon_mailbox0_r(void)
 {
         return 0x00110040U;
@@ -288,6 +308,14 @@ static inline u32 pgsp_falcon_engctl_r(void)
 {
         return 0x001100a4U;
 }
+static inline u32 pgsp_falcon_engctl_switch_context_true_f(void)
+{
+        return 0x8U;
+}
+static inline u32 pgsp_falcon_engctl_switch_context_false_f(void)
+{
+        return 0x0U;
+}
 static inline u32 pgsp_falcon_cpuctl_r(void)
 {
         return 0x00110100U;