diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-06-07 01:56:11 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-07-19 02:41:54 -0400 |
commit | 4df5427c15e28a3bd131a4bdaed413de2a9a5e99 (patch) | |
tree | 2d270dc69779449c4d6a3b5ca2871fdad0ff665f /drivers/gpu/nvgpu/include | |
parent | 68b65f642ab49e8d30a17da04c053673e49e6d24 (diff) |
gpu: nvgpu: gv11b: init perf related gr ops
Implement gv11b specific perf gr ops
JIRA GPUT19X-49
Bug 200311674
Change-Id: Ia65fe84df6e38e25f87d2c1b21c04b518c334d42
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1497402
GVS: Gerrit_Virtual_Submit
Reviewed-by: Tushar Kashalikar <tkashalikar@nvidia.com>
Tested-by: Tushar Kashalikar <tkashalikar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 152 |
1 files changed, 152 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index c9dbee52..153aef2f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | |||
@@ -3998,6 +3998,158 @@ static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m(void) | |||
3998 | { | 3998 | { |
3999 | return 0x1 << 10; | 3999 | return 0x1 << 10; |
4000 | } | 4000 | } |
4001 | static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel0_r(void) | ||
4002 | { | ||
4003 | return 0x00584200; | ||
4004 | } | ||
4005 | static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel1_r(void) | ||
4006 | { | ||
4007 | return 0x00584204; | ||
4008 | } | ||
4009 | static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control0_r(void) | ||
4010 | { | ||
4011 | return 0x00584208; | ||
4012 | } | ||
4013 | static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control1_r(void) | ||
4014 | { | ||
4015 | return 0x00584210; | ||
4016 | } | ||
4017 | static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control2_r(void) | ||
4018 | { | ||
4019 | return 0x00584214; | ||
4020 | } | ||
4021 | static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control3_r(void) | ||
4022 | { | ||
4023 | return 0x00584218; | ||
4024 | } | ||
4025 | static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control4_r(void) | ||
4026 | { | ||
4027 | return 0x0058421c; | ||
4028 | } | ||
4029 | static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control5_r(void) | ||
4030 | { | ||
4031 | return 0x0058420c; | ||
4032 | } | ||
4033 | static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter0_control_r(void) | ||
4034 | { | ||
4035 | return 0x00584220; | ||
4036 | } | ||
4037 | static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter1_control_r(void) | ||
4038 | { | ||
4039 | return 0x00584224; | ||
4040 | } | ||
4041 | static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter2_control_r(void) | ||
4042 | { | ||
4043 | return 0x00584228; | ||
4044 | } | ||
4045 | static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter3_control_r(void) | ||
4046 | { | ||
4047 | return 0x0058422c; | ||
4048 | } | ||
4049 | static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter4_control_r(void) | ||
4050 | { | ||
4051 | return 0x00584230; | ||
4052 | } | ||
4053 | static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter5_control_r(void) | ||
4054 | { | ||
4055 | return 0x00584234; | ||
4056 | } | ||
4057 | static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter6_control_r(void) | ||
4058 | { | ||
4059 | return 0x00584238; | ||
4060 | } | ||
4061 | static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter7_control_r(void) | ||
4062 | { | ||
4063 | return 0x0058423c; | ||
4064 | } | ||
4065 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter_status_s0_r(void) | ||
4066 | { | ||
4067 | return 0x00584600; | ||
4068 | } | ||
4069 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter_status_s1_r(void) | ||
4070 | { | ||
4071 | return 0x00584604; | ||
4072 | } | ||
4073 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s0_r(void) | ||
4074 | { | ||
4075 | return 0x00584624; | ||
4076 | } | ||
4077 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s0_r(void) | ||
4078 | { | ||
4079 | return 0x00584628; | ||
4080 | } | ||
4081 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s0_r(void) | ||
4082 | { | ||
4083 | return 0x0058462c; | ||
4084 | } | ||
4085 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s0_r(void) | ||
4086 | { | ||
4087 | return 0x00584630; | ||
4088 | } | ||
4089 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s1_r(void) | ||
4090 | { | ||
4091 | return 0x00584634; | ||
4092 | } | ||
4093 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s1_r(void) | ||
4094 | { | ||
4095 | return 0x00584638; | ||
4096 | } | ||
4097 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s1_r(void) | ||
4098 | { | ||
4099 | return 0x0058463c; | ||
4100 | } | ||
4101 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s1_r(void) | ||
4102 | { | ||
4103 | return 0x00584640; | ||
4104 | } | ||
4105 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s2_r(void) | ||
4106 | { | ||
4107 | return 0x00584644; | ||
4108 | } | ||
4109 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s2_r(void) | ||
4110 | { | ||
4111 | return 0x00584648; | ||
4112 | } | ||
4113 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s2_r(void) | ||
4114 | { | ||
4115 | return 0x0058464c; | ||
4116 | } | ||
4117 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s2_r(void) | ||
4118 | { | ||
4119 | return 0x00584650; | ||
4120 | } | ||
4121 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s3_r(void) | ||
4122 | { | ||
4123 | return 0x00584654; | ||
4124 | } | ||
4125 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s3_r(void) | ||
4126 | { | ||
4127 | return 0x00584658; | ||
4128 | } | ||
4129 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s3_r(void) | ||
4130 | { | ||
4131 | return 0x0058465c; | ||
4132 | } | ||
4133 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s3_r(void) | ||
4134 | { | ||
4135 | return 0x00584660; | ||
4136 | } | ||
4137 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter4_r(void) | ||
4138 | { | ||
4139 | return 0x00584614; | ||
4140 | } | ||
4141 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter5_r(void) | ||
4142 | { | ||
4143 | return 0x00584618; | ||
4144 | } | ||
4145 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter6_r(void) | ||
4146 | { | ||
4147 | return 0x0058461c; | ||
4148 | } | ||
4149 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter7_r(void) | ||
4150 | { | ||
4151 | return 0x00584620; | ||
4152 | } | ||
4001 | static inline u32 gr_fe_pwr_mode_r(void) | 4153 | static inline u32 gr_fe_pwr_mode_r(void) |
4002 | { | 4154 | { |
4003 | return 0x00404170; | 4155 | return 0x00404170; |