gpu: nvgpu: falcon engine EMEM queue support

-Removed _dmem postfix to some functions which
 can be common for DMEM & EMEM queue, and
 made changes as needed.
-Defined flcn_queue_push_emem() &
 flcn_queue_pop_emem() functions to
 to read/write queue data to/from EMEM
-Defined flcn_queue_init_emem_queue()
 function to assign EMEM specific functions
 to support EMEM queue type.
-Defined QUEUE_TYPE_DMEM to support
 DMEM based queue.
-Defined QUEUE_TYPE_EMEM to support
 EMEM based queue.
-Modified nvgpu_flcn_queue_init() to call queue
 type flcn_queue_init_dmem/emem_queue()
 function to assign its ops.

JIRA NVGPU-1161

Change-Id: I06333fa318b7ca4137c977ad63f5a857e7b36cc8
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1841084
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 5 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/falcon.h b/drivers/gpu/nvgpu/include/nvgpu/falcon.h
index cf15061d..4fc97ee8 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/falcon.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/falcon.h
@@ -84,7 +84,7 @@
 #define FALCON_MAILBOX_0        0x0
 #define FALCON_MAILBOX_1        0x1
 #define FALCON_MAILBOX_COUNT 0x02
-#define FALCON_BLOCK_SIZE 0x100
+#define FALCON_BLOCK_SIZE 0x100U
 
 #define GET_IMEM_TAG(IMEM_ADDR) (IMEM_ADDR >> 8)
 
@@ -168,6 +168,10 @@ struct gk20a;
 struct nvgpu_falcon;
 struct nvgpu_falcon_bl_info;
 
+/* Queue Type */
+#define QUEUE_TYPE_DMEM 0x0U
+#define QUEUE_TYPE_EMEM 0x1U
+
 struct nvgpu_falcon_queue {
 
         /* Queue Type (queue_type) */