gpu: nvgpu: fix TSG enable sequence

Due to a h/w bug in Maxwell and Pascal we first need to enable all channels with
NEXT and CTX_RELOAD set in a TSG, and then rest of the channels should be
enabled
Add this sequence to gk20a_tsg_enable()

Add new APIs to enable/disable scheduling of TSG runlist
gk20a_fifo_enable_tsg_sched()
gk20a_fifo_disble_tsg_sched()

Add new APIs to check if channel has NEXT or CTX_RELOAD set
gk20a_fifo_channel_status_is_next()
gk20a_fifo_channel_status_is_ctx_reload()

Bug 1739362

Change-Id: I4891cbd7f22ebc1e0bf32c52801002cdc259dbe1
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1560636
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

4 files changed, 142 insertions, 6 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ccsr_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ccsr_gk20a.h
index 4877e4a8..c6f792e7 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ccsr_gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ccsr_gk20a.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2012-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -114,6 +114,42 @@ static inline u32 ccsr_channel_status_v(u32 r)
 {
         return (r >> 24) & 0xf;
 }
+static inline u32 ccsr_channel_status_pending_ctx_reload_v(void)
+{
+        return 0x00000002;
+}
+static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void)
+{
+        return 0x00000004;
+}
+static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void)
+{
+        return 0x0000000a;
+}
+static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void)
+{
+        return 0x0000000b;
+}
+static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void)
+{
+        return 0x0000000c;
+}
+static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void)
+{
+        return 0x0000000d;
+}
+static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void)
+{
+        return 0x0000000e;
+}
+static inline u32 ccsr_channel_next_v(u32 r)
+{
+        return (r >> 1) & 0x1;
+}
+static inline u32 ccsr_channel_next_true_v(void)
+{
+        return 0x00000001;
+}
 static inline u32 ccsr_channel_busy_v(u32 r)
 {
         return (r >> 28) & 0x1;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ccsr_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ccsr_gm20b.h
index 2fdf73ae..3f5d312f 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ccsr_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ccsr_gm20b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -110,6 +110,42 @@ static inline u32 ccsr_channel_status_v(u32 r)
 {
         return (r >> 24) & 0xf;
 }
+static inline u32 ccsr_channel_status_pending_ctx_reload_v(void)
+{
+        return 0x00000002;
+}
+static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void)
+{
+        return 0x00000004;
+}
+static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void)
+{
+        return 0x0000000a;
+}
+static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void)
+{
+        return 0x0000000b;
+}
+static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void)
+{
+        return 0x0000000c;
+}
+static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void)
+{
+        return 0x0000000d;
+}
+static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void)
+{
+        return 0x0000000e;
+}
+static inline u32 ccsr_channel_next_v(u32 r)
+{
+        return (r >> 1) & 0x1;
+}
+static inline u32 ccsr_channel_next_true_v(void)
+{
+        return 0x00000001;
+}
 static inline u32 ccsr_channel_busy_v(u32 r)
 {
         return (r >> 28) & 0x1;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ccsr_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ccsr_gp106.h
index 65146d39..13bd4251 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ccsr_gp106.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ccsr_gp106.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -114,12 +114,40 @@ static inline u32 ccsr_channel_status_pending_ctx_reload_v(void)
 {
         return 0x00000002;
 }
-static inline u32 ccsr_channel_busy_v(u32 r)
+static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void)
 {
-        return (r >> 28) & 0x1;
+        return 0x00000004;
+}
+static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void)
+{
+        return 0x0000000a;
+}
+static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void)
+{
+        return 0x0000000b;
+}
+static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void)
+{
+        return 0x0000000c;
+}
+static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void)
+{
+        return 0x0000000d;
+}
+static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void)
+{
+        return 0x0000000e;
 }
 static inline u32 ccsr_channel_next_v(u32 r)
 {
         return (r >> 1) & 0x1;
 }
+static inline u32 ccsr_channel_next_true_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 ccsr_channel_busy_v(u32 r)
+{
+        return (r >> 28) & 0x1;
+}
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ccsr_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ccsr_gp10b.h
index 99398961..33c83c80 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ccsr_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ccsr_gp10b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -110,6 +110,42 @@ static inline u32 ccsr_channel_status_v(u32 r)
 {
         return (r >> 24) & 0xf;
 }
+static inline u32 ccsr_channel_status_pending_ctx_reload_v(void)
+{
+        return 0x00000002;
+}
+static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void)
+{
+        return 0x00000004;
+}
+static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void)
+{
+        return 0x0000000a;
+}
+static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void)
+{
+        return 0x0000000b;
+}
+static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void)
+{
+        return 0x0000000c;
+}
+static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void)
+{
+        return 0x0000000d;
+}
+static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void)
+{
+        return 0x0000000e;
+}
+static inline u32 ccsr_channel_next_v(u32 r)
+{
+        return (r >> 1) & 0x1;
+}
+static inline u32 ccsr_channel_next_true_v(void)
+{
+        return 0x00000001;
+}
 static inline u32 ccsr_channel_busy_v(u32 r)
 {
         return (r >> 28) & 0x1;