diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-03-09 01:34:49 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-04-12 18:33:50 -0400 |
commit | 457f176785af5c8821889d00d89db05bbaf8f772 (patch) | |
tree | d4b7913ffc728c1bda19a70746d758df3ff2f7a0 /drivers/gpu/nvgpu/include | |
parent | fbce374aa0f6101d27ca5b3de97905d2798c6f04 (diff) |
gpu: nvgpu: gv11b: init handle sched_error & ctxsw_timout ops
- detect and decode sched_error type. Any sched error starting with xxx_* is
not supported in h/w and should never be seen by s/w
- for bad_tsg sched error, preempt all runlists to recover as faulted ch/tsg
is unknown. For other errors, just report error.
- ctxsw timeout is not part of sched error fifo interrupt. A new
fifo interrupt, ctxsw timeout is added in gv11b. Add s/w handling.
Bug 1856152
JIRA GPUT19X-74
Change-Id: I474e1a3cda29a450691fe2ea1dc1e239ce57df1a
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1317615
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h | 104 |
1 files changed, 104 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h index f05df49e..dbcb02c8 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h | |||
@@ -230,6 +230,10 @@ static inline u32 fifo_intr_0_channel_intr_pending_f(void) | |||
230 | { | 230 | { |
231 | return 0x80000000; | 231 | return 0x80000000; |
232 | } | 232 | } |
233 | static inline u32 fifo_intr_0_ctxsw_timeout_pending_f(void) | ||
234 | { | ||
235 | return 0x2; | ||
236 | } | ||
233 | static inline u32 fifo_intr_en_0_r(void) | 237 | static inline u32 fifo_intr_en_0_r(void) |
234 | { | 238 | { |
235 | return 0x00002140; | 239 | return 0x00002140; |
@@ -242,6 +246,10 @@ static inline u32 fifo_intr_en_0_sched_error_m(void) | |||
242 | { | 246 | { |
243 | return 0x1 << 8; | 247 | return 0x1 << 8; |
244 | } | 248 | } |
249 | static inline u32 fifo_intr_en_0_ctxsw_timeout_pending_f(void) | ||
250 | { | ||
251 | return 0x2; | ||
252 | } | ||
245 | static inline u32 fifo_intr_en_1_r(void) | 253 | static inline u32 fifo_intr_en_1_r(void) |
246 | { | 254 | { |
247 | return 0x00002528; | 255 | return 0x00002528; |
@@ -266,6 +274,82 @@ static inline u32 fifo_intr_chsw_error_r(void) | |||
266 | { | 274 | { |
267 | return 0x0000256c; | 275 | return 0x0000256c; |
268 | } | 276 | } |
277 | static inline u32 fifo_intr_ctxsw_timeout_r(void) | ||
278 | { | ||
279 | return 0x00002a30; | ||
280 | } | ||
281 | static inline u32 fifo_intr_ctxsw_timeout_engine_f(u32 v, u32 i) | ||
282 | { | ||
283 | return (v & 0x1) << (0 + i*1); | ||
284 | } | ||
285 | static inline u32 fifo_intr_ctxsw_timeout_engine_v(u32 r, u32 i) | ||
286 | { | ||
287 | return (r >> (0 + i*1)) & 0x1; | ||
288 | } | ||
289 | static inline u32 fifo_intr_ctxsw_timeout_engine__size_1_v(void) | ||
290 | { | ||
291 | return 0x00000020; | ||
292 | } | ||
293 | static inline u32 fifo_intr_ctxsw_timeout_engine_pending_v(void) | ||
294 | { | ||
295 | return 0x00000001; | ||
296 | } | ||
297 | static inline u32 fifo_intr_ctxsw_timeout_engine_pending_f(u32 i) | ||
298 | { | ||
299 | return 0x1 << (0 + i*1); | ||
300 | } | ||
301 | static inline u32 fifo_intr_ctxsw_timeout_info_r(u32 i) | ||
302 | { | ||
303 | return 0x00003200 + i*4; | ||
304 | } | ||
305 | static inline u32 fifo_intr_ctxsw_timeout_info__size_1_v(void) | ||
306 | { | ||
307 | return 0x00000004; | ||
308 | } | ||
309 | static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_v(u32 r) | ||
310 | { | ||
311 | return (r >> 0) & 0x3; | ||
312 | } | ||
313 | static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_load_v(void) | ||
314 | { | ||
315 | return 0x00000001; | ||
316 | } | ||
317 | static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_save_v(void) | ||
318 | { | ||
319 | return 0x00000002; | ||
320 | } | ||
321 | static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_switch_v(void) | ||
322 | { | ||
323 | return 0x00000003; | ||
324 | } | ||
325 | static inline u32 fifo_intr_ctxsw_timeout_info_prev_tsgid_v(u32 r) | ||
326 | { | ||
327 | return (r >> 4) & 0xfff; | ||
328 | } | ||
329 | static inline u32 fifo_intr_ctxsw_timeout_info_next_tsgid_v(u32 r) | ||
330 | { | ||
331 | return (r >> 16) & 0xfff; | ||
332 | } | ||
333 | static inline u32 fifo_intr_ctxsw_timeout_info_status_v(u32 r) | ||
334 | { | ||
335 | return (r >> 28) & 0x3; | ||
336 | } | ||
337 | static inline u32 fifo_intr_ctxsw_timeout_info_status_awaiting_ack_v(void) | ||
338 | { | ||
339 | return 0x00000000; | ||
340 | } | ||
341 | static inline u32 fifo_intr_ctxsw_timeout_info_status_eng_was_reset_v(void) | ||
342 | { | ||
343 | return 0x00000001; | ||
344 | } | ||
345 | static inline u32 fifo_intr_ctxsw_timeout_info_status_ack_received_v(void) | ||
346 | { | ||
347 | return 0x00000002; | ||
348 | } | ||
349 | static inline u32 fifo_intr_ctxsw_timeout_info_status_dropped_timeout_v(void) | ||
350 | { | ||
351 | return 0x00000003; | ||
352 | } | ||
269 | static inline u32 fifo_intr_pbdma_id_r(void) | 353 | static inline u32 fifo_intr_pbdma_id_r(void) |
270 | { | 354 | { |
271 | return 0x000025a0; | 355 | return 0x000025a0; |
@@ -450,6 +534,26 @@ static inline u32 fifo_engine_status_ctxsw_in_progress_f(void) | |||
450 | { | 534 | { |
451 | return 0x8000; | 535 | return 0x8000; |
452 | } | 536 | } |
537 | static inline u32 fifo_eng_ctxsw_timeout_r(void) | ||
538 | { | ||
539 | return 0x00002a0c; | ||
540 | } | ||
541 | static inline u32 fifo_eng_ctxsw_timeout_period_f(u32 v) | ||
542 | { | ||
543 | return (v & 0x7fffffff) << 0; | ||
544 | } | ||
545 | static inline u32 fifo_eng_ctxsw_timeout_period_v(u32 r) | ||
546 | { | ||
547 | return (r >> 0) & 0x7fffffff; | ||
548 | } | ||
549 | static inline u32 fifo_eng_ctxsw_timeout_detection_f(u32 v) | ||
550 | { | ||
551 | return (v & 0x1) << 31; | ||
552 | } | ||
553 | static inline u32 fifo_eng_ctxsw_timeout_detection_enabled_f(void) | ||
554 | { | ||
555 | return 0x80000000; | ||
556 | } | ||
453 | static inline u32 fifo_pbdma_status_r(u32 i) | 557 | static inline u32 fifo_pbdma_status_r(u32 i) |
454 | { | 558 | { |
455 | return 0x00003080 + i*4; | 559 | return 0x00003080 + i*4; |