diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2017-05-09 06:19:43 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-06-09 14:13:54 -0400 |
commit | 40ca7cc573430ca4e21fdec4a44394c09d615846 (patch) | |
tree | e4ee884dd8863d9928b34c7b0bf7468f2903c6b1 /drivers/gpu/nvgpu/include | |
parent | 821d1cab904d055264bc5d62b0c0d5187417ff13 (diff) |
gpu: nvgpu: reorganize PMU IPC
- Moved PMU IPC related code to
drivers/gpu/nvgpu/common/pmu/pmu_ipc.c file,
-Below is the list which are moved
seq
mutex
queue
cmd/msg post & process
event handling
NVGPU-56
Change-Id: Ic380faa27de4e5574d5b22500125e86027fd4b5d
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1478167
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/pmu.h | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmu.h index 687e00ae..f447e910 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu.h | |||
@@ -115,6 +115,15 @@ enum { | |||
115 | typedef void (*pmu_callback)(struct gk20a *, struct pmu_msg *, void *, u32, | 115 | typedef void (*pmu_callback)(struct gk20a *, struct pmu_msg *, void *, u32, |
116 | u32); | 116 | u32); |
117 | 117 | ||
118 | struct pmu_payload { | ||
119 | struct { | ||
120 | void *buf; | ||
121 | u32 offset; | ||
122 | u32 size; | ||
123 | u32 fb_size; | ||
124 | } in, out; | ||
125 | }; | ||
126 | |||
118 | struct pmu_ucode_desc { | 127 | struct pmu_ucode_desc { |
119 | u32 descriptor_size; | 128 | u32 descriptor_size; |
120 | u32 image_size; | 129 | u32 image_size; |
@@ -326,4 +335,33 @@ struct nvgpu_pmu { | |||
326 | struct nvgpu_firmware *fw; | 335 | struct nvgpu_firmware *fw; |
327 | }; | 336 | }; |
328 | 337 | ||
338 | /* PMU IPC Methods */ | ||
339 | void nvgpu_pmu_seq_init(struct nvgpu_pmu *pmu); | ||
340 | |||
341 | int nvgpu_pmu_mutex_acquire(struct nvgpu_pmu *pmu, u32 id, u32 *token); | ||
342 | int nvgpu_pmu_mutex_release(struct nvgpu_pmu *pmu, u32 id, u32 *token); | ||
343 | |||
344 | int nvgpu_pmu_queue_init(struct nvgpu_pmu *pmu, u32 id, | ||
345 | union pmu_init_msg_pmu *init); | ||
346 | bool nvgpu_pmu_queue_is_empty(struct nvgpu_pmu *pmu, struct pmu_queue *queue); | ||
347 | |||
348 | /* send a cmd to pmu */ | ||
349 | int gk20a_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd, | ||
350 | struct pmu_msg *msg, struct pmu_payload *payload, | ||
351 | u32 queue_id, pmu_callback callback, void *cb_param, | ||
352 | u32 *seq_desc, unsigned long timeout); | ||
353 | |||
354 | int nvgpu_pmu_process_message(struct nvgpu_pmu *pmu); | ||
355 | |||
356 | /* perfmon */ | ||
357 | int nvgpu_pmu_init_perfmon(struct nvgpu_pmu *pmu); | ||
358 | int nvgpu_pmu_handle_perfmon_event(struct nvgpu_pmu *pmu, | ||
359 | struct pmu_perfmon_msg *msg); | ||
360 | int nvgpu_pmu_handle_therm_event(struct nvgpu_pmu *pmu, | ||
361 | struct nv_pmu_therm_msg *msg); | ||
362 | |||
363 | /* PMU init */ | ||
364 | int nvgpu_pmu_process_init_msg(struct nvgpu_pmu *pmu, | ||
365 | struct pmu_msg *msg); | ||
366 | |||
329 | #endif /* __NVGPU_PMU_H__ */ | 367 | #endif /* __NVGPU_PMU_H__ */ |