gpu: nvgpu: gv10x therm boardobj support

- Added support for below multiple therm sensor device & defined macros
   GPC_TSOSC
   GPC SCI
   HBM2_SITE
   HBM2_COMBINED
- Added PMU interface for listed therm sensor device
- Added nvgpu interface for listed therm sensor device
- Added construct boardobj support for listed therm sensor device
  & called to update nvgpu interface.
- Updated devinit_get_therm_device_table() to read sensor info from
  therm device table from vbios table & construct respective
  therm device boardobj using construct_therm_device_*()
  based on class_id param read from vbios table.
- Updated RPC handler to handle THERM ack request
- Updated gv100 therm ops "get_internal_sensor_limits"
  to point to gp106_get_internal_sensor_limits()

Change-Id: I4b4ed501d0625cb8fc7b300c820622e40ae59fe6
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1676785
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaikundanathan S <vaikuns@nvidia.com>
Tested-by: Vaikundanathan S <vaikuns@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2 files changed, 28 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/bios.h b/drivers/gpu/nvgpu/include/nvgpu/bios.h
index 0619fcb9..0323dce4 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/bios.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/bios.h
@@ -890,7 +890,12 @@ struct therm_device_1x_entry {
         u8 flags;
 } ;
 
-#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU                               0x01
+#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_INVALID            0x00
+#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU                        0x01
+#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU_GPC_TSOSC      0x02
+#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU_GPC_SCI        0x03
+#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_HBM2_SITE          0x70
+#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_HBM2_COMBINED      0x71
 
 #define NV_VBIOS_THERM_DEVICE_1X_ENTRY_PARAM0_I2C_DEVICE_INDEX_MASK        0xFF
 #define NV_VBIOS_THERM_DEVICE_1X_ENTRY_PARAM0_I2C_DEVICE_INDEX_SHIFT          0
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifthermsensor.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifthermsensor.h
index 994cd5b7..8f2a8584 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifthermsensor.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifthermsensor.h
@@ -41,15 +41,37 @@ struct nv_pmu_therm_therm_device_boardobj_set {
         struct nv_pmu_boardobj super;
 };
 
+struct nv_pmu_therm_therm_device_gpu_gpc_tsosc_boardobj_set {
+        struct nv_pmu_therm_therm_device_boardobj_set super;
+        u8 gpc_tsosc_idx;
+};
+
+struct nv_pmu_therm_therm_device_gpu_sci_boardobj_set {
+        struct nv_pmu_therm_therm_device_boardobj_set super;
+};
+
 struct nv_pmu_therm_therm_device_i2c_boardobj_set {
         struct nv_pmu_therm_therm_device_boardobj_set super;
         u8 i2c_dev_idx;
 };
 
+struct nv_pmu_therm_therm_device_hbm2_site_boardobj_set {
+        struct nv_pmu_therm_therm_device_boardobj_set super;
+        u8 site_idx;
+};
+
+struct nv_pmu_therm_therm_device_hbm2_combined_boardobj_set {
+        struct nv_pmu_therm_therm_device_boardobj_set super;
+};
+
 union nv_pmu_therm_therm_device_boardobj_set_union {
         struct nv_pmu_boardobj board_obj;
         struct nv_pmu_therm_therm_device_boardobj_set therm_device;
+        struct nv_pmu_therm_therm_device_gpu_gpc_tsosc_boardobj_set gpu_gpc_tsosc;
+        struct nv_pmu_therm_therm_device_gpu_sci_boardobj_set gpu_sci;
         struct nv_pmu_therm_therm_device_i2c_boardobj_set i2c;
+        struct nv_pmu_therm_therm_device_hbm2_site_boardobj_set hbm2_site;
+        struct nv_pmu_therm_therm_device_hbm2_combined_boardobj_set hbm2_combined;
 };
 
 NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(therm, therm_device);