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author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2017-09-20 02:01:08 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-09-25 03:19:03 -0400 |
commit | 39eb00dedac630f7945e22875d822a76d0caa578 (patch) | |
tree | 59c82a6c2a041ebf5c61d13dcde0dd217f6b7522 /drivers/gpu/nvgpu/include | |
parent | 4d5216922b288a70f7434ac8f7c6c8274cc1462b (diff) |
gpu: nvgpu: gv11b faclon hw header update
- Update CPUCTL register to add soft/hard reset support
- Added debug registers
JIRA NVGPU-56
Change-Id: Id867dd3a6085131917c2ada88f9899e415348038
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1564156
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h | 60 |
1 files changed, 48 insertions, 12 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h index 6bdc5fd1..711c2b4b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h | |||
@@ -290,6 +290,14 @@ static inline u32 falcon_falcon_cpuctl_startcpu_f(u32 v) | |||
290 | { | 290 | { |
291 | return (v & 0x1) << 1; | 291 | return (v & 0x1) << 1; |
292 | } | 292 | } |
293 | static inline u32 falcon_falcon_cpuctl_sreset_f(u32 v) | ||
294 | { | ||
295 | return (v & 0x1) << 2; | ||
296 | } | ||
297 | static inline u32 falcon_falcon_cpuctl_hreset_f(u32 v) | ||
298 | { | ||
299 | return (v & 0x1) << 3; | ||
300 | } | ||
293 | static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v) | 301 | static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v) |
294 | { | 302 | { |
295 | return (v & 0x1) << 4; | 303 | return (v & 0x1) << 4; |
@@ -302,6 +310,10 @@ static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r) | |||
302 | { | 310 | { |
303 | return (r >> 4) & 0x1; | 311 | return (r >> 4) & 0x1; |
304 | } | 312 | } |
313 | static inline u32 falcon_falcon_cpuctl_stopped_m(void) | ||
314 | { | ||
315 | return 0x1 << 5; | ||
316 | } | ||
305 | static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v) | 317 | static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v) |
306 | { | 318 | { |
307 | return (v & 0x1) << 6; | 319 | return (v & 0x1) << 6; |
@@ -390,18 +402,6 @@ static inline u32 falcon_falcon_hwcfg_dmem_size_v(u32 r) | |||
390 | { | 402 | { |
391 | return (r >> 9) & 0x1ff; | 403 | return (r >> 9) & 0x1ff; |
392 | } | 404 | } |
393 | static inline u32 falcon_falcon_hwcfg1_r(void) | ||
394 | { | ||
395 | return 0x0000012c; | ||
396 | } | ||
397 | static inline u32 falcon_falcon_hwcfg1_core_rev_v(u32 r) | ||
398 | { | ||
399 | return (r >> 0) & 0xf; | ||
400 | } | ||
401 | static inline u32 falcon_falcon_hwcfg1_security_model_v(u32 r) | ||
402 | { | ||
403 | return (r >> 4) & 0x3; | ||
404 | } | ||
405 | static inline u32 falcon_falcon_dmatrfbase_r(void) | 405 | static inline u32 falcon_falcon_dmatrfbase_r(void) |
406 | { | 406 | { |
407 | return 0x00000110; | 407 | return 0x00000110; |
@@ -438,6 +438,42 @@ static inline u32 falcon_falcon_dmatrffboffs_r(void) | |||
438 | { | 438 | { |
439 | return 0x0000011c; | 439 | return 0x0000011c; |
440 | } | 440 | } |
441 | static inline u32 falcon_falcon_imctl_debug_r(void) | ||
442 | { | ||
443 | return 0x0000015c; | ||
444 | } | ||
445 | static inline u32 falcon_falcon_imctl_debug_addr_blk_f(u32 v) | ||
446 | { | ||
447 | return (v & 0xffffff) << 0; | ||
448 | } | ||
449 | static inline u32 falcon_falcon_imctl_debug_cmd_f(u32 v) | ||
450 | { | ||
451 | return (v & 0x7) << 24; | ||
452 | } | ||
453 | static inline u32 falcon_falcon_imstat_r(void) | ||
454 | { | ||
455 | return 0x00000144; | ||
456 | } | ||
457 | static inline u32 falcon_falcon_traceidx_r(void) | ||
458 | { | ||
459 | return 0x00000148; | ||
460 | } | ||
461 | static inline u32 falcon_falcon_traceidx_maxidx_v(u32 r) | ||
462 | { | ||
463 | return (r >> 16) & 0xff; | ||
464 | } | ||
465 | static inline u32 falcon_falcon_traceidx_idx_f(u32 v) | ||
466 | { | ||
467 | return (v & 0xff) << 0; | ||
468 | } | ||
469 | static inline u32 falcon_falcon_tracepc_r(void) | ||
470 | { | ||
471 | return 0x0000014c; | ||
472 | } | ||
473 | static inline u32 falcon_falcon_tracepc_pc_v(u32 r) | ||
474 | { | ||
475 | return (r >> 0) & 0xffffff; | ||
476 | } | ||
441 | static inline u32 falcon_falcon_exterraddr_r(void) | 477 | static inline u32 falcon_falcon_exterraddr_r(void) |
442 | { | 478 | { |
443 | return 0x00000168; | 479 | return 0x00000168; |