diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2017-02-06 06:19:24 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-02-10 12:43:46 -0500 |
commit | 3885fe099af0bda910ac8ee64f2cd1a5bbea3ab0 (patch) | |
tree | 602ead38e7631ce81db7e600802fdac0aba49974 /drivers/gpu/nvgpu/include | |
parent | 8da422ac577338ecb2d4114e1d8d5f36cf4cab78 (diff) |
gpu: nvgpu: move pmuif/* to drivers/gpu/nvgpu/include/nvgpu
Moved pmuif/* headers to drivers/gpu/nvgpu/include/nvgpu folder
to support cross platform feature implementation.
Made changes to files which accessed include pmuif/* to reflect
pmuif/* movement changes.
Deleted includes of gk20a.h/pmu_gk20a.h from pmuif/*.h files.
Jira NVGPU-19
Change-Id: Iace4e107c24bdaff08a407eae3b147959173e485
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1299823
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/include')
18 files changed, 3394 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_acr.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_acr.h new file mode 100644 index 00000000..440ffbaa --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_acr.h | |||
@@ -0,0 +1,104 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | #ifndef _GPMUIFACR_H_ | ||
14 | #define _GPMUIFACR_H_ | ||
15 | |||
16 | /* ACR Commands/Message structures */ | ||
17 | |||
18 | enum { | ||
19 | PMU_ACR_CMD_ID_INIT_WPR_REGION = 0x0, | ||
20 | PMU_ACR_CMD_ID_BOOTSTRAP_FALCON, | ||
21 | PMU_ACR_CMD_ID_RESERVED, | ||
22 | PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS, | ||
23 | }; | ||
24 | |||
25 | /* | ||
26 | * Initializes the WPR region details | ||
27 | */ | ||
28 | struct pmu_acr_cmd_init_wpr_details { | ||
29 | u8 cmd_type; | ||
30 | u32 regionid; | ||
31 | u32 wproffset; | ||
32 | |||
33 | }; | ||
34 | |||
35 | /* | ||
36 | * falcon ID to bootstrap | ||
37 | */ | ||
38 | struct pmu_acr_cmd_bootstrap_falcon { | ||
39 | u8 cmd_type; | ||
40 | u32 flags; | ||
41 | u32 falconid; | ||
42 | }; | ||
43 | |||
44 | /* | ||
45 | * falcon ID to bootstrap | ||
46 | */ | ||
47 | struct pmu_acr_cmd_bootstrap_multiple_falcons { | ||
48 | u8 cmd_type; | ||
49 | u32 flags; | ||
50 | u32 falconidmask; | ||
51 | u32 usevamask; | ||
52 | struct falc_u64 wprvirtualbase; | ||
53 | }; | ||
54 | |||
55 | #define PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_NO 1 | ||
56 | #define PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES 0 | ||
57 | |||
58 | |||
59 | struct pmu_acr_cmd { | ||
60 | union { | ||
61 | u8 cmd_type; | ||
62 | struct pmu_acr_cmd_bootstrap_falcon bootstrap_falcon; | ||
63 | struct pmu_acr_cmd_init_wpr_details init_wpr; | ||
64 | struct pmu_acr_cmd_bootstrap_multiple_falcons boot_falcons; | ||
65 | }; | ||
66 | }; | ||
67 | |||
68 | /* acr messages */ | ||
69 | |||
70 | /* | ||
71 | * returns the WPR region init information | ||
72 | */ | ||
73 | #define PMU_ACR_MSG_ID_INIT_WPR_REGION 0 | ||
74 | |||
75 | /* | ||
76 | * Returns the Bootstrapped falcon ID to RM | ||
77 | */ | ||
78 | #define PMU_ACR_MSG_ID_BOOTSTRAP_FALCON 1 | ||
79 | |||
80 | /* | ||
81 | * Returns the WPR init status | ||
82 | */ | ||
83 | #define PMU_ACR_SUCCESS 0 | ||
84 | #define PMU_ACR_ERROR 1 | ||
85 | |||
86 | /* | ||
87 | * PMU notifies about bootstrap status of falcon | ||
88 | */ | ||
89 | struct pmu_acr_msg_bootstrap_falcon { | ||
90 | u8 msg_type; | ||
91 | union { | ||
92 | u32 errorcode; | ||
93 | u32 falconid; | ||
94 | }; | ||
95 | }; | ||
96 | |||
97 | struct pmu_acr_msg { | ||
98 | union { | ||
99 | u8 msg_type; | ||
100 | struct pmu_acr_msg_bootstrap_falcon acrmsg; | ||
101 | }; | ||
102 | }; | ||
103 | |||
104 | #endif /* _GPMUIFACR_H_ */ | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_ap.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_ap.h new file mode 100644 index 00000000..7e2f546c --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_ap.h | |||
@@ -0,0 +1,247 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | #ifndef _GPMUIFAP_H_ | ||
14 | #define _GPMUIFAP_H_ | ||
15 | |||
16 | /* PMU Command/Message Interfaces for Adaptive Power */ | ||
17 | /* Macro to get Histogram index */ | ||
18 | #define PMU_AP_HISTOGRAM(idx) (idx) | ||
19 | #define PMU_AP_HISTOGRAM_CONT (4) | ||
20 | |||
21 | /* Total number of histogram bins */ | ||
22 | #define PMU_AP_CFG_HISTOGRAM_BIN_N (16) | ||
23 | |||
24 | /* Mapping between Idle counters and histograms */ | ||
25 | #define PMU_AP_IDLE_MASK_HIST_IDX_0 (2) | ||
26 | #define PMU_AP_IDLE_MASK_HIST_IDX_1 (3) | ||
27 | #define PMU_AP_IDLE_MASK_HIST_IDX_2 (5) | ||
28 | #define PMU_AP_IDLE_MASK_HIST_IDX_3 (6) | ||
29 | |||
30 | |||
31 | /* Mapping between AP_CTRLs and Histograms */ | ||
32 | #define PMU_AP_HISTOGRAM_IDX_GRAPHICS (PMU_AP_HISTOGRAM(1)) | ||
33 | |||
34 | /* Mapping between AP_CTRLs and Idle counters */ | ||
35 | #define PMU_AP_IDLE_MASK_GRAPHICS (PMU_AP_IDLE_MASK_HIST_IDX_1) | ||
36 | |||
37 | /* Adaptive Power Controls (AP_CTRL) */ | ||
38 | enum { | ||
39 | PMU_AP_CTRL_ID_GRAPHICS = 0x0, | ||
40 | PMU_AP_CTRL_ID_MAX, | ||
41 | }; | ||
42 | |||
43 | /* AP_CTRL Statistics */ | ||
44 | struct pmu_ap_ctrl_stat { | ||
45 | /* | ||
46 | * Represents whether AP is active or not | ||
47 | */ | ||
48 | u8 b_active; | ||
49 | |||
50 | /* Idle filter represented by histogram bin index */ | ||
51 | u8 idle_filter_x; | ||
52 | u8 rsvd[2]; | ||
53 | |||
54 | /* Total predicted power saving cycles. */ | ||
55 | s32 power_saving_h_cycles; | ||
56 | |||
57 | /* Counts how many times AP gave us -ve power benefits. */ | ||
58 | u32 bad_decision_count; | ||
59 | |||
60 | /* | ||
61 | * Number of times ap structure needs to skip AP iterations | ||
62 | * KICK_CTRL from kernel updates this parameter. | ||
63 | */ | ||
64 | u32 skip_count; | ||
65 | u8 bin[PMU_AP_CFG_HISTOGRAM_BIN_N]; | ||
66 | }; | ||
67 | |||
68 | /* Parameters initialized by INITn APCTRL command */ | ||
69 | struct pmu_ap_ctrl_init_params { | ||
70 | /* Minimum idle filter value in Us */ | ||
71 | u32 min_idle_filter_us; | ||
72 | |||
73 | /* | ||
74 | * Minimum Targeted Saving in Us. AP will update idle thresholds only | ||
75 | * if power saving achieved by updating idle thresholds is greater than | ||
76 | * Minimum targeted saving. | ||
77 | */ | ||
78 | u32 min_target_saving_us; | ||
79 | |||
80 | /* Minimum targeted residency of power feature in Us */ | ||
81 | u32 power_break_even_us; | ||
82 | |||
83 | /* | ||
84 | * Maximum number of allowed power feature cycles per sample. | ||
85 | * | ||
86 | * We are allowing at max "pgPerSampleMax" cycles in one iteration of AP | ||
87 | * AKA pgPerSampleMax in original algorithm. | ||
88 | */ | ||
89 | u32 cycles_per_sample_max; | ||
90 | }; | ||
91 | |||
92 | /* AP Commands/Message structures */ | ||
93 | |||
94 | /* | ||
95 | * Structure for Generic AP Commands | ||
96 | */ | ||
97 | struct pmu_ap_cmd_common { | ||
98 | u8 cmd_type; | ||
99 | u16 cmd_id; | ||
100 | }; | ||
101 | |||
102 | /* | ||
103 | * Structure for INIT AP command | ||
104 | */ | ||
105 | struct pmu_ap_cmd_init { | ||
106 | u8 cmd_type; | ||
107 | u16 cmd_id; | ||
108 | u8 rsvd; | ||
109 | u32 pg_sampling_period_us; | ||
110 | }; | ||
111 | |||
112 | /* | ||
113 | * Structure for Enable/Disable ApCtrl Commands | ||
114 | */ | ||
115 | struct pmu_ap_cmd_enable_ctrl { | ||
116 | u8 cmd_type; | ||
117 | u16 cmd_id; | ||
118 | |||
119 | u8 ctrl_id; | ||
120 | }; | ||
121 | |||
122 | struct pmu_ap_cmd_disable_ctrl { | ||
123 | u8 cmd_type; | ||
124 | u16 cmd_id; | ||
125 | |||
126 | u8 ctrl_id; | ||
127 | }; | ||
128 | |||
129 | /* | ||
130 | * Structure for INIT command | ||
131 | */ | ||
132 | struct pmu_ap_cmd_init_ctrl { | ||
133 | u8 cmd_type; | ||
134 | u16 cmd_id; | ||
135 | u8 ctrl_id; | ||
136 | struct pmu_ap_ctrl_init_params params; | ||
137 | }; | ||
138 | |||
139 | struct pmu_ap_cmd_init_and_enable_ctrl { | ||
140 | u8 cmd_type; | ||
141 | u16 cmd_id; | ||
142 | u8 ctrl_id; | ||
143 | struct pmu_ap_ctrl_init_params params; | ||
144 | }; | ||
145 | |||
146 | /* | ||
147 | * Structure for KICK_CTRL command | ||
148 | */ | ||
149 | struct pmu_ap_cmd_kick_ctrl { | ||
150 | u8 cmd_type; | ||
151 | u16 cmd_id; | ||
152 | u8 ctrl_id; | ||
153 | |||
154 | u32 skip_count; | ||
155 | }; | ||
156 | |||
157 | /* | ||
158 | * Structure for PARAM command | ||
159 | */ | ||
160 | struct pmu_ap_cmd_param { | ||
161 | u8 cmd_type; | ||
162 | u16 cmd_id; | ||
163 | u8 ctrl_id; | ||
164 | |||
165 | u32 data; | ||
166 | }; | ||
167 | |||
168 | /* | ||
169 | * Defines for AP commands | ||
170 | */ | ||
171 | enum { | ||
172 | PMU_AP_CMD_ID_INIT = 0x0, | ||
173 | PMU_AP_CMD_ID_INIT_AND_ENABLE_CTRL, | ||
174 | PMU_AP_CMD_ID_ENABLE_CTRL, | ||
175 | PMU_AP_CMD_ID_DISABLE_CTRL, | ||
176 | PMU_AP_CMD_ID_KICK_CTRL, | ||
177 | }; | ||
178 | |||
179 | /* | ||
180 | * AP Command | ||
181 | */ | ||
182 | union pmu_ap_cmd { | ||
183 | u8 cmd_type; | ||
184 | struct pmu_ap_cmd_common cmn; | ||
185 | struct pmu_ap_cmd_init init; | ||
186 | struct pmu_ap_cmd_init_and_enable_ctrl init_and_enable_ctrl; | ||
187 | struct pmu_ap_cmd_enable_ctrl enable_ctrl; | ||
188 | struct pmu_ap_cmd_disable_ctrl disable_ctrl; | ||
189 | struct pmu_ap_cmd_kick_ctrl kick_ctrl; | ||
190 | }; | ||
191 | |||
192 | /* | ||
193 | * Structure for generic AP Message | ||
194 | */ | ||
195 | struct pmu_ap_msg_common { | ||
196 | u8 msg_type; | ||
197 | u16 msg_id; | ||
198 | }; | ||
199 | |||
200 | /* | ||
201 | * Structure for INIT_ACK Message | ||
202 | */ | ||
203 | struct pmu_ap_msg_init_ack { | ||
204 | u8 msg_type; | ||
205 | u16 msg_id; | ||
206 | u8 ctrl_id; | ||
207 | u32 stats_dmem_offset; | ||
208 | }; | ||
209 | |||
210 | /* | ||
211 | * Defines for AP messages | ||
212 | */ | ||
213 | enum { | ||
214 | PMU_AP_MSG_ID_INIT_ACK = 0x0, | ||
215 | }; | ||
216 | |||
217 | /* | ||
218 | * AP Message | ||
219 | */ | ||
220 | union pmu_ap_msg { | ||
221 | u8 msg_type; | ||
222 | struct pmu_ap_msg_common cmn; | ||
223 | struct pmu_ap_msg_init_ack init_ack; | ||
224 | }; | ||
225 | |||
226 | /* | ||
227 | * Adaptive Power Controller | ||
228 | */ | ||
229 | struct ap_ctrl { | ||
230 | u32 stats_dmem_offset; | ||
231 | u32 disable_reason_mask; | ||
232 | struct pmu_ap_ctrl_stat stat_cache; | ||
233 | u8 b_ready; | ||
234 | }; | ||
235 | |||
236 | /* | ||
237 | * Adaptive Power structure | ||
238 | * | ||
239 | * ap structure provides generic infrastructure to make any power feature | ||
240 | * adaptive. | ||
241 | */ | ||
242 | struct pmu_ap { | ||
243 | u32 supported_mask; | ||
244 | struct ap_ctrl ap_ctrl[PMU_AP_CTRL_ID_MAX]; | ||
245 | }; | ||
246 | |||
247 | #endif /* _GPMUIFAP_H_*/ | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_cmn.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_cmn.h new file mode 100644 index 00000000..1d200129 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_cmn.h | |||
@@ -0,0 +1,121 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | #ifndef _GPMUIFCMN_H_ | ||
14 | #define _GPMUIFCMN_H_ | ||
15 | |||
16 | /* | ||
17 | * Defines the logical queue IDs that must be used when submitting | ||
18 | * commands to the PMU | ||
19 | */ | ||
20 | /* write by sw, read by pmu, protected by sw mutex lock */ | ||
21 | #define PMU_COMMAND_QUEUE_HPQ 0 | ||
22 | /* write by sw, read by pmu, protected by sw mutex lock */ | ||
23 | #define PMU_COMMAND_QUEUE_LPQ 1 | ||
24 | /* read/write by sw/hw, protected by hw pmu mutex, id = 2 */ | ||
25 | #define PMU_COMMAND_QUEUE_BIOS 2 | ||
26 | /* read/write by sw/hw, protected by hw pmu mutex, id = 3 */ | ||
27 | #define PMU_COMMAND_QUEUE_SMI 3 | ||
28 | /* write by pmu, read by sw, accessed by interrupt handler, no lock */ | ||
29 | #define PMU_MESSAGE_QUEUE 4 | ||
30 | #define PMU_QUEUE_COUNT 5 | ||
31 | |||
32 | #define PMU_IS_COMMAND_QUEUE(id) \ | ||
33 | ((id) < PMU_MESSAGE_QUEUE) | ||
34 | |||
35 | #define PMU_IS_SW_COMMAND_QUEUE(id) \ | ||
36 | (((id) == PMU_COMMAND_QUEUE_HPQ) || \ | ||
37 | ((id) == PMU_COMMAND_QUEUE_LPQ)) | ||
38 | |||
39 | #define PMU_IS_MESSAGE_QUEUE(id) \ | ||
40 | ((id) == PMU_MESSAGE_QUEUE) | ||
41 | |||
42 | enum { | ||
43 | OFLAG_READ = 0, | ||
44 | OFLAG_WRITE | ||
45 | }; | ||
46 | |||
47 | #define QUEUE_SET (true) | ||
48 | #define QUEUE_GET (false) | ||
49 | |||
50 | #define QUEUE_ALIGNMENT (4) | ||
51 | |||
52 | /* An enumeration containing all valid logical mutex identifiers */ | ||
53 | enum { | ||
54 | PMU_MUTEX_ID_RSVD1 = 0, | ||
55 | PMU_MUTEX_ID_GPUSER, | ||
56 | PMU_MUTEX_ID_QUEUE_BIOS, | ||
57 | PMU_MUTEX_ID_QUEUE_SMI, | ||
58 | PMU_MUTEX_ID_GPMUTEX, | ||
59 | PMU_MUTEX_ID_I2C, | ||
60 | PMU_MUTEX_ID_RMLOCK, | ||
61 | PMU_MUTEX_ID_MSGBOX, | ||
62 | PMU_MUTEX_ID_FIFO, | ||
63 | PMU_MUTEX_ID_PG, | ||
64 | PMU_MUTEX_ID_GR, | ||
65 | PMU_MUTEX_ID_CLK, | ||
66 | PMU_MUTEX_ID_RSVD6, | ||
67 | PMU_MUTEX_ID_RSVD7, | ||
68 | PMU_MUTEX_ID_RSVD8, | ||
69 | PMU_MUTEX_ID_RSVD9, | ||
70 | PMU_MUTEX_ID_INVALID | ||
71 | }; | ||
72 | |||
73 | #define PMU_MUTEX_ID_IS_VALID(id) \ | ||
74 | ((id) < PMU_MUTEX_ID_INVALID) | ||
75 | |||
76 | #define PMU_INVALID_MUTEX_OWNER_ID (0) | ||
77 | |||
78 | /* | ||
79 | * The PMU's frame-buffer interface block has several slots/indices | ||
80 | * which can be bound to support DMA to various surfaces in memory | ||
81 | */ | ||
82 | enum { | ||
83 | PMU_DMAIDX_UCODE = 0, | ||
84 | PMU_DMAIDX_VIRT = 1, | ||
85 | PMU_DMAIDX_PHYS_VID = 2, | ||
86 | PMU_DMAIDX_PHYS_SYS_COH = 3, | ||
87 | PMU_DMAIDX_PHYS_SYS_NCOH = 4, | ||
88 | PMU_DMAIDX_RSVD = 5, | ||
89 | PMU_DMAIDX_PELPG = 6, | ||
90 | PMU_DMAIDX_END = 7 | ||
91 | }; | ||
92 | |||
93 | /* | ||
94 | * Falcon PMU DMA's minimum size in bytes. | ||
95 | */ | ||
96 | #define PMU_DMA_MIN_READ_SIZE_BYTES 16 | ||
97 | #define PMU_DMA_MIN_WRITE_SIZE_BYTES 4 | ||
98 | |||
99 | #define PMU_FB_COPY_RW_ALIGNMENT \ | ||
100 | ((PMU_DMA_MIN_READ_SIZE_BYTES > PMU_DMA_MIN_WRITE_SIZE_BYTES) ? \ | ||
101 | PMU_DMA_MIN_READ_SIZE_BYTES : PMU_DMA_MIN_WRITE_SIZE_BYTES) | ||
102 | |||
103 | /* | ||
104 | * Macros to make aligned versions of RM_PMU_XXX structures. PMU needs aligned | ||
105 | * data structures to issue DMA read/write operations. | ||
106 | */ | ||
107 | #define NV_PMU_MAKE_ALIGNED_STRUCT(name, size) \ | ||
108 | union name##_aligned { \ | ||
109 | struct name data; \ | ||
110 | u8 pad[ALIGN_UP(sizeof(struct name), \ | ||
111 | (PMU_FB_COPY_RW_ALIGNMENT))]; \ | ||
112 | } | ||
113 | |||
114 | #define NV_PMU_MAKE_ALIGNED_UNION(name, size) \ | ||
115 | union name##_aligned { \ | ||
116 | union name data; \ | ||
117 | u8 pad[ALIGN_UP(sizeof(union name), \ | ||
118 | (PMU_FB_COPY_RW_ALIGNMENT))]; \ | ||
119 | } | ||
120 | |||
121 | #endif /* _GPMUIFCMN_H_*/ | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h new file mode 100644 index 00000000..098d0305 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h | |||
@@ -0,0 +1,178 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | #ifndef _GPMUIFPERFMON_H_ | ||
14 | #define _GPMUIFPERFMON_H_ | ||
15 | |||
16 | /*perfmon task defines*/ | ||
17 | |||
18 | #define PMU_DOMAIN_GROUP_PSTATE 0 | ||
19 | #define PMU_DOMAIN_GROUP_GPC2CLK 1 | ||
20 | #define PMU_DOMAIN_GROUP_NUM 2 | ||
21 | |||
22 | #define PMU_PERFMON_FLAG_ENABLE_INCREASE (0x00000001) | ||
23 | #define PMU_PERFMON_FLAG_ENABLE_DECREASE (0x00000002) | ||
24 | #define PMU_PERFMON_FLAG_CLEAR_PREV (0x00000004) | ||
25 | |||
26 | enum pmu_perfmon_cmd_start_fields { | ||
27 | COUNTER_ALLOC | ||
28 | }; | ||
29 | |||
30 | enum { | ||
31 | PMU_PERFMON_CMD_ID_START = 0, | ||
32 | PMU_PERFMON_CMD_ID_STOP = 1, | ||
33 | PMU_PERFMON_CMD_ID_INIT = 2 | ||
34 | }; | ||
35 | |||
36 | struct pmu_perfmon_counter_v0 { | ||
37 | u8 index; | ||
38 | u8 flags; | ||
39 | u8 group_id; | ||
40 | u8 valid; | ||
41 | u16 upper_threshold; /* units of 0.01% */ | ||
42 | u16 lower_threshold; /* units of 0.01% */ | ||
43 | }; | ||
44 | |||
45 | struct pmu_perfmon_counter_v2 { | ||
46 | u8 index; | ||
47 | u8 flags; | ||
48 | u8 group_id; | ||
49 | u8 valid; | ||
50 | u16 upper_threshold; /* units of 0.01% */ | ||
51 | u16 lower_threshold; /* units of 0.01% */ | ||
52 | u32 scale; | ||
53 | }; | ||
54 | |||
55 | struct pmu_perfmon_cmd_start_v3 { | ||
56 | u8 cmd_type; | ||
57 | u8 group_id; | ||
58 | u8 state_id; | ||
59 | u8 flags; | ||
60 | struct pmu_allocation_v3 counter_alloc; | ||
61 | }; | ||
62 | |||
63 | struct pmu_perfmon_cmd_start_v2 { | ||
64 | u8 cmd_type; | ||
65 | u8 group_id; | ||
66 | u8 state_id; | ||
67 | u8 flags; | ||
68 | struct pmu_allocation_v2 counter_alloc; | ||
69 | }; | ||
70 | |||
71 | struct pmu_perfmon_cmd_start_v1 { | ||
72 | u8 cmd_type; | ||
73 | u8 group_id; | ||
74 | u8 state_id; | ||
75 | u8 flags; | ||
76 | struct pmu_allocation_v1 counter_alloc; | ||
77 | }; | ||
78 | |||
79 | struct pmu_perfmon_cmd_start_v0 { | ||
80 | u8 cmd_type; | ||
81 | u8 group_id; | ||
82 | u8 state_id; | ||
83 | u8 flags; | ||
84 | struct pmu_allocation_v0 counter_alloc; | ||
85 | }; | ||
86 | |||
87 | struct pmu_perfmon_cmd_stop { | ||
88 | u8 cmd_type; | ||
89 | }; | ||
90 | |||
91 | struct pmu_perfmon_cmd_init_v3 { | ||
92 | u8 cmd_type; | ||
93 | u8 to_decrease_count; | ||
94 | u8 base_counter_id; | ||
95 | u32 sample_period_us; | ||
96 | struct pmu_allocation_v3 counter_alloc; | ||
97 | u8 num_counters; | ||
98 | u8 samples_in_moving_avg; | ||
99 | u16 sample_buffer; | ||
100 | }; | ||
101 | |||
102 | struct pmu_perfmon_cmd_init_v2 { | ||
103 | u8 cmd_type; | ||
104 | u8 to_decrease_count; | ||
105 | u8 base_counter_id; | ||
106 | u32 sample_period_us; | ||
107 | struct pmu_allocation_v2 counter_alloc; | ||
108 | u8 num_counters; | ||
109 | u8 samples_in_moving_avg; | ||
110 | u16 sample_buffer; | ||
111 | }; | ||
112 | |||
113 | struct pmu_perfmon_cmd_init_v1 { | ||
114 | u8 cmd_type; | ||
115 | u8 to_decrease_count; | ||
116 | u8 base_counter_id; | ||
117 | u32 sample_period_us; | ||
118 | struct pmu_allocation_v1 counter_alloc; | ||
119 | u8 num_counters; | ||
120 | u8 samples_in_moving_avg; | ||
121 | u16 sample_buffer; | ||
122 | }; | ||
123 | |||
124 | struct pmu_perfmon_cmd_init_v0 { | ||
125 | u8 cmd_type; | ||
126 | u8 to_decrease_count; | ||
127 | u8 base_counter_id; | ||
128 | u32 sample_period_us; | ||
129 | struct pmu_allocation_v0 counter_alloc; | ||
130 | u8 num_counters; | ||
131 | u8 samples_in_moving_avg; | ||
132 | u16 sample_buffer; | ||
133 | }; | ||
134 | |||
135 | struct pmu_perfmon_cmd { | ||
136 | union { | ||
137 | u8 cmd_type; | ||
138 | struct pmu_perfmon_cmd_start_v0 start_v0; | ||
139 | struct pmu_perfmon_cmd_start_v1 start_v1; | ||
140 | struct pmu_perfmon_cmd_start_v2 start_v2; | ||
141 | struct pmu_perfmon_cmd_start_v3 start_v3; | ||
142 | struct pmu_perfmon_cmd_stop stop; | ||
143 | struct pmu_perfmon_cmd_init_v0 init_v0; | ||
144 | struct pmu_perfmon_cmd_init_v1 init_v1; | ||
145 | struct pmu_perfmon_cmd_init_v2 init_v2; | ||
146 | struct pmu_perfmon_cmd_init_v3 init_v3; | ||
147 | }; | ||
148 | }; | ||
149 | |||
150 | struct pmu_zbc_cmd { | ||
151 | u8 cmd_type; | ||
152 | u8 pad; | ||
153 | u16 entry_mask; | ||
154 | }; | ||
155 | |||
156 | /* PERFMON MSG */ | ||
157 | enum { | ||
158 | PMU_PERFMON_MSG_ID_INCREASE_EVENT = 0, | ||
159 | PMU_PERFMON_MSG_ID_DECREASE_EVENT = 1, | ||
160 | PMU_PERFMON_MSG_ID_INIT_EVENT = 2, | ||
161 | PMU_PERFMON_MSG_ID_ACK = 3 | ||
162 | }; | ||
163 | |||
164 | struct pmu_perfmon_msg_generic { | ||
165 | u8 msg_type; | ||
166 | u8 state_id; | ||
167 | u8 group_id; | ||
168 | u8 data; | ||
169 | }; | ||
170 | |||
171 | struct pmu_perfmon_msg { | ||
172 | union { | ||
173 | u8 msg_type; | ||
174 | struct pmu_perfmon_msg_generic gen; | ||
175 | }; | ||
176 | }; | ||
177 | |||
178 | #endif /* _GPMUIFPERFMON_H_ */ | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h new file mode 100644 index 00000000..8c71e2a2 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h | |||
@@ -0,0 +1,311 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | #ifndef _GPMUIFPG_H_ | ||
14 | #define _GPMUIFPG_H_ | ||
15 | |||
16 | #include "gpmuif_ap.h" | ||
17 | #include "gpmuif_pg_rppg.h" | ||
18 | |||
19 | /*PG defines*/ | ||
20 | |||
21 | /* Identifier for each PG */ | ||
22 | #define PMU_PG_ELPG_ENGINE_ID_GRAPHICS (0x00000000) | ||
23 | #define PMU_PG_ELPG_ENGINE_ID_MS (0x00000004) | ||
24 | #define PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE (0x00000005) | ||
25 | #define PMU_PG_ELPG_ENGINE_MAX PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE | ||
26 | |||
27 | /* PG message */ | ||
28 | enum { | ||
29 | PMU_PG_ELPG_MSG_INIT_ACK, | ||
30 | PMU_PG_ELPG_MSG_DISALLOW_ACK, | ||
31 | PMU_PG_ELPG_MSG_ALLOW_ACK, | ||
32 | PMU_PG_ELPG_MSG_FREEZE_ACK, | ||
33 | PMU_PG_ELPG_MSG_FREEZE_ABORT, | ||
34 | PMU_PG_ELPG_MSG_UNFREEZE_ACK, | ||
35 | }; | ||
36 | |||
37 | struct pmu_pg_msg_elpg_msg { | ||
38 | u8 msg_type; | ||
39 | u8 engine_id; | ||
40 | u16 msg; | ||
41 | }; | ||
42 | |||
43 | enum { | ||
44 | PMU_PG_STAT_MSG_RESP_DMEM_OFFSET = 0, | ||
45 | }; | ||
46 | |||
47 | struct pmu_pg_msg_stat { | ||
48 | u8 msg_type; | ||
49 | u8 engine_id; | ||
50 | u16 sub_msg_id; | ||
51 | u32 data; | ||
52 | }; | ||
53 | |||
54 | enum { | ||
55 | PMU_PG_MSG_ENG_BUF_LOADED, | ||
56 | PMU_PG_MSG_ENG_BUF_UNLOADED, | ||
57 | PMU_PG_MSG_ENG_BUF_FAILED, | ||
58 | }; | ||
59 | |||
60 | struct pmu_pg_msg_eng_buf_stat { | ||
61 | u8 msg_type; | ||
62 | u8 engine_id; | ||
63 | u8 buf_idx; | ||
64 | u8 status; | ||
65 | }; | ||
66 | |||
67 | struct pmu_pg_msg { | ||
68 | union { | ||
69 | u8 msg_type; | ||
70 | struct pmu_pg_msg_elpg_msg elpg_msg; | ||
71 | struct pmu_pg_msg_stat stat; | ||
72 | struct pmu_pg_msg_eng_buf_stat eng_buf_stat; | ||
73 | /* TBD: other pg messages */ | ||
74 | union pmu_ap_msg ap_msg; | ||
75 | struct nv_pmu_rppg_msg rppg_msg; | ||
76 | }; | ||
77 | }; | ||
78 | |||
79 | /* PG commands */ | ||
80 | enum { | ||
81 | PMU_PG_ELPG_CMD_INIT, | ||
82 | PMU_PG_ELPG_CMD_DISALLOW, | ||
83 | PMU_PG_ELPG_CMD_ALLOW, | ||
84 | PMU_PG_ELPG_CMD_FREEZE, | ||
85 | PMU_PG_ELPG_CMD_UNFREEZE, | ||
86 | }; | ||
87 | |||
88 | enum { | ||
89 | PMU_PG_CMD_ID_ELPG_CMD = 0, | ||
90 | PMU_PG_CMD_ID_ENG_BUF_LOAD, | ||
91 | PMU_PG_CMD_ID_ENG_BUF_UNLOAD, | ||
92 | PMU_PG_CMD_ID_PG_STAT, | ||
93 | PMU_PG_CMD_ID_PG_LOG_INIT, | ||
94 | PMU_PG_CMD_ID_PG_LOG_FLUSH, | ||
95 | PMU_PG_CMD_ID_PG_PARAM, | ||
96 | PMU_PG_CMD_ID_ELPG_INIT, | ||
97 | PMU_PG_CMD_ID_ELPG_POLL_CTXSAVE, | ||
98 | PMU_PG_CMD_ID_ELPG_ABORT_POLL, | ||
99 | PMU_PG_CMD_ID_ELPG_PWR_UP, | ||
100 | PMU_PG_CMD_ID_ELPG_DISALLOW, | ||
101 | PMU_PG_CMD_ID_ELPG_ALLOW, | ||
102 | PMU_PG_CMD_ID_AP, | ||
103 | RM_PMU_PG_CMD_ID_PSI, | ||
104 | RM_PMU_PG_CMD_ID_CG, | ||
105 | PMU_PG_CMD_ID_ZBC_TABLE_UPDATE, | ||
106 | PMU_PG_CMD_ID_PWR_RAIL_GATE_DISABLE = 0x20, | ||
107 | PMU_PG_CMD_ID_PWR_RAIL_GATE_ENABLE, | ||
108 | PMU_PG_CMD_ID_PWR_RAIL_SMU_MSG_DISABLE, | ||
109 | PMU_PMU_PG_CMD_ID_RPPG = 0x24, | ||
110 | }; | ||
111 | |||
112 | enum { | ||
113 | PMU_PG_STAT_CMD_ALLOC_DMEM = 0, | ||
114 | }; | ||
115 | |||
116 | #define PMU_PG_PARAM_CMD_GR_INIT_PARAM 0x0 | ||
117 | #define PMU_PG_PARAM_CMD_MS_INIT_PARAM 0x01 | ||
118 | #define PMU_PG_PARAM_CMD_MCLK_CHANGE 0x04 | ||
119 | #define PMU_PG_PARAM_CMD_POST_INIT 0x06 | ||
120 | |||
121 | #define PMU_PG_FEATURE_GR_SDIV_SLOWDOWN_ENABLED (1 << 0) | ||
122 | #define PMU_PG_FEATURE_GR_POWER_GATING_ENABLED (1 << 2) | ||
123 | #define PMU_PG_FEATURE_GR_RPPG_ENABLED (1 << 3) | ||
124 | |||
125 | #define NVGPU_PMU_GR_FEATURE_MASK_RPPG (1 << 3) | ||
126 | #define NVGPU_PMU_GR_FEATURE_MASK_ALL \ | ||
127 | ( \ | ||
128 | NVGPU_PMU_GR_FEATURE_MASK_RPPG \ | ||
129 | ) | ||
130 | |||
131 | #define NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING (1 << 0) | ||
132 | #define NVGPU_PMU_MS_FEATURE_MASK_SW_ASR (1 << 1) | ||
133 | #define NVGPU_PMU_MS_FEATURE_MASK_RPPG (1 << 8) | ||
134 | #define NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING (1 << 5) | ||
135 | |||
136 | #define NVGPU_PMU_MS_FEATURE_MASK_ALL \ | ||
137 | ( \ | ||
138 | NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING |\ | ||
139 | NVGPU_PMU_MS_FEATURE_MASK_SW_ASR |\ | ||
140 | NVGPU_PMU_MS_FEATURE_MASK_RPPG |\ | ||
141 | NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING \ | ||
142 | ) | ||
143 | |||
144 | |||
145 | struct pmu_pg_cmd_elpg_cmd { | ||
146 | u8 cmd_type; | ||
147 | u8 engine_id; | ||
148 | u16 cmd; | ||
149 | }; | ||
150 | |||
151 | struct pmu_pg_cmd_eng_buf_load_v0 { | ||
152 | u8 cmd_type; | ||
153 | u8 engine_id; | ||
154 | u8 buf_idx; | ||
155 | u8 pad; | ||
156 | u16 buf_size; | ||
157 | u32 dma_base; | ||
158 | u8 dma_offset; | ||
159 | u8 dma_idx; | ||
160 | }; | ||
161 | |||
162 | struct pmu_pg_cmd_eng_buf_load_v1 { | ||
163 | u8 cmd_type; | ||
164 | u8 engine_id; | ||
165 | u8 buf_idx; | ||
166 | u8 pad; | ||
167 | struct flcn_mem_desc { | ||
168 | struct falc_u64 dma_addr; | ||
169 | u16 dma_size; | ||
170 | u8 dma_idx; | ||
171 | } dma_desc; | ||
172 | }; | ||
173 | |||
174 | struct pmu_pg_cmd_eng_buf_load_v2 { | ||
175 | u8 cmd_type; | ||
176 | u8 engine_id; | ||
177 | u8 buf_idx; | ||
178 | u8 pad; | ||
179 | struct flcn_mem_desc_v0 dma_desc; | ||
180 | }; | ||
181 | |||
182 | struct pmu_pg_cmd_gr_init_param { | ||
183 | u8 cmd_type; | ||
184 | u16 sub_cmd_id; | ||
185 | u8 featuremask; | ||
186 | }; | ||
187 | |||
188 | struct pmu_pg_cmd_ms_init_param { | ||
189 | u8 cmd_type; | ||
190 | u16 cmd_id; | ||
191 | u8 psi; | ||
192 | u8 idle_flipped_test_enabled; | ||
193 | u16 psiSettleTimeUs; | ||
194 | u8 rsvd[2]; | ||
195 | u32 support_mask; | ||
196 | u32 abort_timeout_us; | ||
197 | }; | ||
198 | |||
199 | struct pmu_pg_cmd_mclk_change { | ||
200 | u8 cmd_type; | ||
201 | u16 cmd_id; | ||
202 | u8 rsvd; | ||
203 | u32 data; | ||
204 | }; | ||
205 | |||
206 | #define PG_VOLT_RAIL_IDX_MAX 2 | ||
207 | |||
208 | struct pmu_pg_volt_rail { | ||
209 | u8 volt_rail_idx; | ||
210 | u8 sleep_volt_dev_idx; | ||
211 | u8 sleep_vfe_idx; | ||
212 | u32 sleep_voltage_uv; | ||
213 | u32 therm_vid0_cache; | ||
214 | u32 therm_vid1_cache; | ||
215 | }; | ||
216 | |||
217 | struct pmu_pg_cmd_post_init_param { | ||
218 | u8 cmd_type; | ||
219 | u16 cmd_id; | ||
220 | struct pmu_pg_volt_rail pg_volt_rail[PG_VOLT_RAIL_IDX_MAX]; | ||
221 | }; | ||
222 | |||
223 | struct pmu_pg_cmd_stat { | ||
224 | u8 cmd_type; | ||
225 | u8 engine_id; | ||
226 | u16 sub_cmd_id; | ||
227 | u32 data; | ||
228 | }; | ||
229 | |||
230 | struct pmu_pg_cmd { | ||
231 | union { | ||
232 | u8 cmd_type; | ||
233 | struct pmu_pg_cmd_elpg_cmd elpg_cmd; | ||
234 | struct pmu_pg_cmd_eng_buf_load_v0 eng_buf_load_v0; | ||
235 | struct pmu_pg_cmd_eng_buf_load_v1 eng_buf_load_v1; | ||
236 | struct pmu_pg_cmd_eng_buf_load_v2 eng_buf_load_v2; | ||
237 | struct pmu_pg_cmd_stat stat; | ||
238 | struct pmu_pg_cmd_gr_init_param gr_init_param; | ||
239 | struct pmu_pg_cmd_ms_init_param ms_init_param; | ||
240 | struct pmu_pg_cmd_mclk_change mclk_change; | ||
241 | struct pmu_pg_cmd_post_init_param post_init; | ||
242 | /* TBD: other pg commands */ | ||
243 | union pmu_ap_cmd ap_cmd; | ||
244 | struct nv_pmu_rppg_cmd rppg_cmd; | ||
245 | }; | ||
246 | }; | ||
247 | |||
248 | /* Statistics structure for PG features */ | ||
249 | struct pmu_pg_stats_v2 { | ||
250 | u32 entry_count; | ||
251 | u32 exit_count; | ||
252 | u32 abort_count; | ||
253 | u32 detection_count; | ||
254 | u32 prevention_activate_count; | ||
255 | u32 prevention_deactivate_count; | ||
256 | u32 powered_up_time_us; | ||
257 | u32 entry_latency_us; | ||
258 | u32 exit_latency_us; | ||
259 | u32 resident_time_us; | ||
260 | u32 entry_latency_avg_us; | ||
261 | u32 exit_latency_avg_us; | ||
262 | u32 entry_latency_max_us; | ||
263 | u32 exit_latency_max_us; | ||
264 | u32 total_sleep_time_us; | ||
265 | u32 total_non_sleep_time_us; | ||
266 | }; | ||
267 | |||
268 | struct pmu_pg_stats_v1 { | ||
269 | /* Number of time PMU successfully engaged sleep state */ | ||
270 | u32 entry_count; | ||
271 | /* Number of time PMU exit sleep state */ | ||
272 | u32 exit_count; | ||
273 | /* Number of time PMU aborted in entry sequence */ | ||
274 | u32 abort_count; | ||
275 | /* | ||
276 | * Time for which GPU was neither in Sleep state not | ||
277 | * executing sleep sequence. | ||
278 | */ | ||
279 | u32 poweredup_timeus; | ||
280 | /* Entry and exit latency of current sleep cycle */ | ||
281 | u32 entry_latency_us; | ||
282 | u32 exitlatencyus; | ||
283 | /* Resident time for current sleep cycle. */ | ||
284 | u32 resident_timeus; | ||
285 | /* Rolling average entry and exit latencies */ | ||
286 | u32 entrylatency_avgus; | ||
287 | u32 exitlatency_avgus; | ||
288 | /* Max entry and exit latencies */ | ||
289 | u32 entrylatency_maxus; | ||
290 | u32 exitlatency_maxus; | ||
291 | /* Total time spent in sleep and non-sleep state */ | ||
292 | u32 total_sleep_timeus; | ||
293 | u32 total_nonsleep_timeus; | ||
294 | }; | ||
295 | |||
296 | struct pmu_pg_stats { | ||
297 | u64 pg_entry_start_timestamp; | ||
298 | u64 pg_ingating_start_timestamp; | ||
299 | u64 pg_exit_start_timestamp; | ||
300 | u64 pg_ungating_start_timestamp; | ||
301 | u32 pg_avg_entry_time_us; | ||
302 | u32 pg_ingating_cnt; | ||
303 | u32 pg_ingating_time_us; | ||
304 | u32 pg_avg_exit_time_us; | ||
305 | u32 pg_ungating_count; | ||
306 | u32 pg_ungating_time_us; | ||
307 | u32 pg_gating_cnt; | ||
308 | u32 pg_gating_deny_cnt; | ||
309 | }; | ||
310 | |||
311 | #endif /* _GPMUIFPG_H_*/ | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg_rppg.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg_rppg.h new file mode 100644 index 00000000..d2f23011 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg_rppg.h | |||
@@ -0,0 +1,101 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | #ifndef _GPMUIFRPPG_H_ | ||
14 | #define _GPMUIFRPPG_H_ | ||
15 | |||
16 | #define NV_PMU_RPPG_CTRL_ID_GR (0x0000) | ||
17 | #define NV_PMU_RPPG_CTRL_ID_MS (0x0001) | ||
18 | #define NV_PMU_RPPG_CTRL_ID_DI (0x0002) | ||
19 | #define NV_PMU_RPPG_CTRL_ID_MAX (0x0003) | ||
20 | |||
21 | #define NV_PMU_RPPG_CTRL_MASK_ENABLE_ALL (BIT(NV_PMU_RPPG_CTRL_ID_GR) |\ | ||
22 | BIT(NV_PMU_RPPG_CTRL_ID_MS) |\ | ||
23 | BIT(NV_PMU_RPPG_CTRL_ID_DI)) | ||
24 | |||
25 | #define NV_PMU_RPPG_CTRL_MASK_DISABLE_ALL 0 | ||
26 | |||
27 | enum { | ||
28 | NV_PMU_RPPG_DOMAIN_ID_GFX = 0x0, | ||
29 | NV_PMU_RPPG_DOMAIN_ID_NON_GFX, | ||
30 | }; | ||
31 | |||
32 | struct nv_pmu_rppg_ctrl_stats { | ||
33 | u32 entry_count; | ||
34 | u32 exit_count; | ||
35 | }; | ||
36 | |||
37 | struct nv_pmu_rppg_cmd_common { | ||
38 | u8 cmd_type; | ||
39 | u8 cmd_id; | ||
40 | }; | ||
41 | |||
42 | struct nv_pmu_rppg_cmd_init { | ||
43 | u8 cmd_type; | ||
44 | u8 cmd_id; | ||
45 | }; | ||
46 | |||
47 | struct nv_pmu_rppg_cmd_init_ctrl { | ||
48 | u8 cmd_type; | ||
49 | u8 cmd_id; | ||
50 | u8 ctrl_id; | ||
51 | u8 domain_id; | ||
52 | }; | ||
53 | |||
54 | struct nv_pmu_rppg_cmd_stats_reset { | ||
55 | u8 cmd_type; | ||
56 | u8 cmd_id; | ||
57 | u8 ctrl_id; | ||
58 | }; | ||
59 | |||
60 | struct nv_pmu_rppg_cmd { | ||
61 | union { | ||
62 | u8 cmd_type; | ||
63 | struct nv_pmu_rppg_cmd_common cmn; | ||
64 | struct nv_pmu_rppg_cmd_init init; | ||
65 | struct nv_pmu_rppg_cmd_init_ctrl init_ctrl; | ||
66 | struct nv_pmu_rppg_cmd_stats_reset stats_reset; | ||
67 | }; | ||
68 | }; | ||
69 | |||
70 | enum { | ||
71 | NV_PMU_RPPG_CMD_ID_INIT = 0x0, | ||
72 | NV_PMU_RPPG_CMD_ID_INIT_CTRL, | ||
73 | NV_PMU_RPPG_CMD_ID_STATS_RESET, | ||
74 | }; | ||
75 | |||
76 | |||
77 | struct nv_pmu_rppg_msg_common { | ||
78 | u8 msg_type; | ||
79 | u8 msg_id; | ||
80 | }; | ||
81 | |||
82 | struct nv_pmu_rppg_msg_init_ctrl_ack { | ||
83 | u8 msg_type; | ||
84 | u8 msg_id; | ||
85 | u8 ctrl_id; | ||
86 | u32 stats_dmem_offset; | ||
87 | }; | ||
88 | |||
89 | struct nv_pmu_rppg_msg { | ||
90 | union { | ||
91 | u8 msg_type; | ||
92 | struct nv_pmu_rppg_msg_common cmn; | ||
93 | struct nv_pmu_rppg_msg_init_ctrl_ack init_ctrl_ack; | ||
94 | }; | ||
95 | }; | ||
96 | |||
97 | enum { | ||
98 | NV_PMU_RPPG_MSG_ID_INIT_CTRL_ACK = 0x0, | ||
99 | }; | ||
100 | |||
101 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h new file mode 100644 index 00000000..6df92c1d --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h | |||
@@ -0,0 +1,215 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | #ifndef _GPMUIFPMU_H_ | ||
14 | #define _GPMUIFPMU_H_ | ||
15 | |||
16 | #include <nvgpu/flcnif_cmn.h> | ||
17 | #include "gpmuif_cmn.h" | ||
18 | |||
19 | /* Make sure size of this structure is a multiple of 4 bytes */ | ||
20 | struct pmu_cmdline_args_v0 { | ||
21 | u32 cpu_freq_hz; | ||
22 | u32 falc_trace_size; | ||
23 | u32 falc_trace_dma_base; | ||
24 | u32 falc_trace_dma_idx; | ||
25 | struct pmu_mem_v0 gc6_ctx; | ||
26 | }; | ||
27 | |||
28 | struct pmu_cmdline_args_v1 { | ||
29 | u32 cpu_freq_hz; | ||
30 | u32 falc_trace_size; | ||
31 | u32 falc_trace_dma_base; | ||
32 | u32 falc_trace_dma_idx; | ||
33 | u8 secure_mode; | ||
34 | struct pmu_mem_v1 gc6_ctx; | ||
35 | }; | ||
36 | |||
37 | struct pmu_cmdline_args_v2 { | ||
38 | u32 cpu_freq_hz; | ||
39 | u32 falc_trace_size; | ||
40 | u32 falc_trace_dma_base; | ||
41 | u32 falc_trace_dma_idx; | ||
42 | u8 secure_mode; | ||
43 | u8 raise_priv_sec; | ||
44 | struct pmu_mem_v1 gc6_ctx; | ||
45 | }; | ||
46 | |||
47 | struct pmu_cmdline_args_v3 { | ||
48 | u32 reserved; | ||
49 | u32 cpu_freq_hz; | ||
50 | u32 falc_trace_size; | ||
51 | u32 falc_trace_dma_base; | ||
52 | u32 falc_trace_dma_idx; | ||
53 | u8 secure_mode; | ||
54 | u8 raise_priv_sec; | ||
55 | struct pmu_mem_v1 gc6_ctx; | ||
56 | }; | ||
57 | |||
58 | struct pmu_cmdline_args_v4 { | ||
59 | u32 reserved; | ||
60 | u32 cpu_freq_hz; | ||
61 | u32 falc_trace_size; | ||
62 | struct falc_dma_addr dma_addr; | ||
63 | u32 falc_trace_dma_idx; | ||
64 | u8 secure_mode; | ||
65 | u8 raise_priv_sec; | ||
66 | struct pmu_mem_desc_v0 gc6_ctx; | ||
67 | u8 pad; | ||
68 | }; | ||
69 | |||
70 | struct pmu_cmdline_args_v5 { | ||
71 | u32 cpu_freq_hz; | ||
72 | struct flcn_mem_desc_v0 trace_buf; | ||
73 | u8 secure_mode; | ||
74 | u8 raise_priv_sec; | ||
75 | struct flcn_mem_desc_v0 gc6_ctx; | ||
76 | struct flcn_mem_desc_v0 init_data_dma_info; | ||
77 | u32 dummy; | ||
78 | }; | ||
79 | |||
80 | /* GPU ID */ | ||
81 | #define PMU_SHA1_GID_SIGNATURE 0xA7C66AD2 | ||
82 | #define PMU_SHA1_GID_SIGNATURE_SIZE 4 | ||
83 | |||
84 | #define PMU_SHA1_GID_SIZE 16 | ||
85 | |||
86 | struct pmu_sha1_gid { | ||
87 | bool valid; | ||
88 | u8 gid[PMU_SHA1_GID_SIZE]; | ||
89 | }; | ||
90 | |||
91 | struct pmu_sha1_gid_data { | ||
92 | u8 signature[PMU_SHA1_GID_SIGNATURE_SIZE]; | ||
93 | u8 gid[PMU_SHA1_GID_SIZE]; | ||
94 | }; | ||
95 | |||
96 | /* PMU INIT MSG */ | ||
97 | enum { | ||
98 | PMU_INIT_MSG_TYPE_PMU_INIT = 0, | ||
99 | }; | ||
100 | |||
101 | struct pmu_init_msg_pmu_v0 { | ||
102 | u8 msg_type; | ||
103 | u8 pad; | ||
104 | |||
105 | struct { | ||
106 | u16 size; | ||
107 | u16 offset; | ||
108 | u8 index; | ||
109 | u8 pad; | ||
110 | } queue_info[PMU_QUEUE_COUNT]; | ||
111 | |||
112 | u16 sw_managed_area_offset; | ||
113 | u16 sw_managed_area_size; | ||
114 | }; | ||
115 | |||
116 | struct pmu_init_msg_pmu_v1 { | ||
117 | u8 msg_type; | ||
118 | u8 pad; | ||
119 | u16 os_debug_entry_point; | ||
120 | |||
121 | struct { | ||
122 | u16 size; | ||
123 | u16 offset; | ||
124 | u8 index; | ||
125 | u8 pad; | ||
126 | } queue_info[PMU_QUEUE_COUNT]; | ||
127 | |||
128 | u16 sw_managed_area_offset; | ||
129 | u16 sw_managed_area_size; | ||
130 | }; | ||
131 | struct pmu_init_msg_pmu_v2 { | ||
132 | u8 msg_type; | ||
133 | u8 pad; | ||
134 | u16 os_debug_entry_point; | ||
135 | |||
136 | struct { | ||
137 | u16 size; | ||
138 | u16 offset; | ||
139 | u8 index; | ||
140 | u8 pad; | ||
141 | } queue_info[PMU_QUEUE_COUNT]; | ||
142 | |||
143 | u16 sw_managed_area_offset; | ||
144 | u16 sw_managed_area_size; | ||
145 | u8 dummy[18]; | ||
146 | }; | ||
147 | |||
148 | #define PMU_QUEUE_COUNT_FOR_V4 5 | ||
149 | #define PMU_QUEUE_COUNT_FOR_V3 3 | ||
150 | #define PMU_QUEUE_HPQ_IDX_FOR_V3 0 | ||
151 | #define PMU_QUEUE_LPQ_IDX_FOR_V3 1 | ||
152 | #define PMU_QUEUE_MSG_IDX_FOR_V3 2 | ||
153 | struct pmu_init_msg_pmu_v3 { | ||
154 | u8 msg_type; | ||
155 | u8 queue_index[PMU_QUEUE_COUNT_FOR_V3]; | ||
156 | u16 queue_size[PMU_QUEUE_COUNT_FOR_V3]; | ||
157 | u16 queue_offset; | ||
158 | |||
159 | u16 sw_managed_area_offset; | ||
160 | u16 sw_managed_area_size; | ||
161 | |||
162 | u16 os_debug_entry_point; | ||
163 | |||
164 | u8 dummy[18]; | ||
165 | }; | ||
166 | |||
167 | struct pmu_init_msg_pmu_v4 { | ||
168 | u8 msg_type; | ||
169 | u8 queue_index[PMU_QUEUE_COUNT_FOR_V4]; | ||
170 | u16 queue_size[PMU_QUEUE_COUNT_FOR_V4]; | ||
171 | u16 queue_offset; | ||
172 | |||
173 | u16 sw_managed_area_offset; | ||
174 | u16 sw_managed_area_size; | ||
175 | |||
176 | u16 os_debug_entry_point; | ||
177 | |||
178 | u8 dummy[18]; | ||
179 | }; | ||
180 | |||
181 | union pmu_init_msg_pmu { | ||
182 | struct pmu_init_msg_pmu_v0 v0; | ||
183 | struct pmu_init_msg_pmu_v1 v1; | ||
184 | struct pmu_init_msg_pmu_v2 v2; | ||
185 | struct pmu_init_msg_pmu_v3 v3; | ||
186 | struct pmu_init_msg_pmu_v4 v4; | ||
187 | }; | ||
188 | |||
189 | struct pmu_init_msg { | ||
190 | union { | ||
191 | u8 msg_type; | ||
192 | struct pmu_init_msg_pmu_v1 pmu_init_v1; | ||
193 | struct pmu_init_msg_pmu_v0 pmu_init_v0; | ||
194 | struct pmu_init_msg_pmu_v2 pmu_init_v2; | ||
195 | struct pmu_init_msg_pmu_v3 pmu_init_v3; | ||
196 | struct pmu_init_msg_pmu_v4 pmu_init_v4; | ||
197 | }; | ||
198 | }; | ||
199 | |||
200 | /* robust channel (RC) messages */ | ||
201 | enum { | ||
202 | PMU_RC_MSG_TYPE_UNHANDLED_CMD = 0, | ||
203 | }; | ||
204 | |||
205 | struct pmu_rc_msg_unhandled_cmd { | ||
206 | u8 msg_type; | ||
207 | u8 unit_id; | ||
208 | }; | ||
209 | |||
210 | struct pmu_rc_msg { | ||
211 | u8 msg_type; | ||
212 | struct pmu_rc_msg_unhandled_cmd unhandled_cmd; | ||
213 | }; | ||
214 | |||
215 | #endif /* _GPMUIFPMU_H_*/ | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifbios.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifbios.h new file mode 100644 index 00000000..eaa44bc2 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifbios.h | |||
@@ -0,0 +1,41 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | #ifndef _GPMUIFBIOS_H_ | ||
14 | #define _GPMUIFBIOS_H_ | ||
15 | |||
16 | struct nv_pmu_bios_vfield_register_segment_super { | ||
17 | u8 type; | ||
18 | u8 low_bit; | ||
19 | u8 high_bit; | ||
20 | }; | ||
21 | |||
22 | struct nv_pmu_bios_vfield_register_segment_reg { | ||
23 | struct nv_pmu_bios_vfield_register_segment_super super; | ||
24 | u32 addr; | ||
25 | }; | ||
26 | |||
27 | struct nv_pmu_bios_vfield_register_segment_index_reg { | ||
28 | struct nv_pmu_bios_vfield_register_segment_super super; | ||
29 | u32 addr; | ||
30 | u32 reg_index; | ||
31 | u32 index; | ||
32 | }; | ||
33 | |||
34 | union nv_pmu_bios_vfield_register_segment { | ||
35 | struct nv_pmu_bios_vfield_register_segment_super super; | ||
36 | struct nv_pmu_bios_vfield_register_segment_reg reg; | ||
37 | struct nv_pmu_bios_vfield_register_segment_index_reg index_reg; | ||
38 | }; | ||
39 | |||
40 | |||
41 | #endif /* _GPMUIFBIOS_H_*/ | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifboardobj.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifboardobj.h new file mode 100644 index 00000000..8da31469 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifboardobj.h | |||
@@ -0,0 +1,195 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | #ifndef _GPMUIFBOARDOBJ_H_ | ||
14 | #define _GPMUIFBOARDOBJ_H_ | ||
15 | |||
16 | #include <nvgpu/flcnif_cmn.h> | ||
17 | #include "ctrl/ctrlboardobj.h" | ||
18 | |||
19 | /* | ||
20 | * Base structure describing a BOARDOBJ for communication between Kernel and | ||
21 | * PMU. | ||
22 | */ | ||
23 | struct nv_pmu_boardobj { | ||
24 | u8 type; | ||
25 | }; | ||
26 | |||
27 | /* | ||
28 | * Base structure describing a BOARDOBJ for Query interface between Kernel and | ||
29 | * PMU. | ||
30 | */ | ||
31 | struct nv_pmu_boardobj_query { | ||
32 | u8 type; | ||
33 | }; | ||
34 | |||
35 | /* | ||
36 | * Virtual base structure describing a BOARDOBJGRP interface between Kernel and | ||
37 | * PMU. | ||
38 | */ | ||
39 | struct nv_pmu_boardobjgrp_super { | ||
40 | u8 type; | ||
41 | u8 class_id; | ||
42 | u8 obj_slots; | ||
43 | u8 rsvd; | ||
44 | }; | ||
45 | |||
46 | struct nv_pmu_boardobjgrp { | ||
47 | struct nv_pmu_boardobjgrp_super super; | ||
48 | u32 obj_mask; | ||
49 | }; | ||
50 | |||
51 | struct nv_pmu_boardobjgrp_e32 { | ||
52 | struct nv_pmu_boardobjgrp_super super; | ||
53 | struct ctrl_boardobjgrp_mask_e32 obj_mask; | ||
54 | }; | ||
55 | |||
56 | struct nv_pmu_boardobjgrp_e255 { | ||
57 | struct nv_pmu_boardobjgrp_super super; | ||
58 | struct ctrl_boardobjgrp_mask_e255 obj_mask; | ||
59 | }; | ||
60 | |||
61 | struct nv_pmu_boardobj_cmd_grp_payload { | ||
62 | struct pmu_allocation_v3 dmem_buf; | ||
63 | struct flcn_mem_desc_v0 fb; | ||
64 | u8 hdr_size; | ||
65 | u8 entry_size; | ||
66 | }; | ||
67 | |||
68 | struct nv_pmu_boardobj_cmd_grp { | ||
69 | u8 cmd_type; | ||
70 | u8 pad[2]; | ||
71 | u8 class_id; | ||
72 | struct nv_pmu_boardobj_cmd_grp_payload grp; | ||
73 | }; | ||
74 | |||
75 | #define NV_PMU_BOARDOBJ_GRP_ALLOC_OFFSET \ | ||
76 | (NV_OFFSETOF(NV_PMU_BOARDOBJ_CMD_GRP, grp)) | ||
77 | |||
78 | struct nv_pmu_boardobj_cmd { | ||
79 | union { | ||
80 | u8 cmd_type; | ||
81 | struct nv_pmu_boardobj_cmd_grp grp; | ||
82 | struct nv_pmu_boardobj_cmd_grp grp_set; | ||
83 | struct nv_pmu_boardobj_cmd_grp grp_get_status; | ||
84 | }; | ||
85 | }; | ||
86 | |||
87 | struct nv_pmu_boardobj_msg_grp { | ||
88 | u8 msg_type; | ||
89 | bool b_success; | ||
90 | flcn_status flcn_status; | ||
91 | u8 class_id; | ||
92 | }; | ||
93 | |||
94 | struct nv_pmu_boardobj_msg { | ||
95 | union { | ||
96 | u8 msg_type; | ||
97 | struct nv_pmu_boardobj_msg_grp grp; | ||
98 | struct nv_pmu_boardobj_msg_grp grp_set; | ||
99 | struct nv_pmu_boardobj_msg_grp grp_get_status; | ||
100 | }; | ||
101 | }; | ||
102 | |||
103 | /* | ||
104 | * Macro generating structures describing classes which implement | ||
105 | * NV_PMU_BOARDOBJGRP via the NV_PMU_BOARDBOBJ_CMD_GRP SET interface. | ||
106 | * | ||
107 | * @para _eng Name of implementing engine in which this structure is | ||
108 | * found. | ||
109 | * @param _class Class ID of Objects within Board Object Group. | ||
110 | * @param _slots Max number of elements this group can contain. | ||
111 | */ | ||
112 | #define NV_PMU_BOARDOBJ_GRP_SET_MAKE(_eng, _class, _slots) \ | ||
113 | NV_PMU_MAKE_ALIGNED_STRUCT( \ | ||
114 | nv_pmu_##_eng##_##_class##_boardobjgrp_set_header, one_structure); \ | ||
115 | NV_PMU_MAKE_ALIGNED_UNION( \ | ||
116 | nv_pmu_##_eng##_##_class##_boardobj_set_union, one_union); \ | ||
117 | struct nv_pmu_##_eng##_##_class##_boardobj_grp_set { \ | ||
118 | union nv_pmu_##_eng##_##_class##_boardobjgrp_set_header_aligned hdr; \ | ||
119 | union nv_pmu_##_eng##_##_class##_boardobj_set_union_aligned objects[(_slots)];\ | ||
120 | } | ||
121 | |||
122 | /* | ||
123 | * Macro generating structures describing classes which implement | ||
124 | * NV_PMU_BOARDOBJGRP_E32 via the NV_PMU_BOARDBOBJ_CMD_GRP SET interface. | ||
125 | * | ||
126 | * @para _eng Name of implementing engine in which this structure is | ||
127 | * found. | ||
128 | * @param _class Class ID of Objects within Board Object Group. | ||
129 | */ | ||
130 | #define NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(_eng, _class) \ | ||
131 | NV_PMU_BOARDOBJ_GRP_SET_MAKE(_eng, _class, \ | ||
132 | CTRL_BOARDOBJGRP_E32_MAX_OBJECTS) | ||
133 | |||
134 | /* | ||
135 | * Macro generating structures describing classes which implement | ||
136 | * NV_PMU_BOARDOBJGRP_E255 via the NV_PMU_BOARDBOBJ_CMD_GRP SET interface. | ||
137 | * | ||
138 | * @para _eng Name of implementing engine in which this structure is | ||
139 | * found. | ||
140 | * @param _class Class ID of Objects within Board Object Group. | ||
141 | */ | ||
142 | #define NV_PMU_BOARDOBJ_GRP_SET_MAKE_E255(_eng, _class) \ | ||
143 | NV_PMU_BOARDOBJ_GRP_SET_MAKE(_eng, _class, \ | ||
144 | CTRL_BOARDOBJGRP_E255_MAX_OBJECTS) | ||
145 | |||
146 | /* | ||
147 | * Macro generating structures for querying dynamic state for classes which | ||
148 | * implement NV_PMU_BOARDOBJGRP via the NV_PMU_BOARDOBJ_CMD_GRP GET_STATUS | ||
149 | * interface. | ||
150 | * | ||
151 | * @para _eng Name of implementing engine in which this structure is | ||
152 | * found. | ||
153 | * @param _class Class ID of Objects within Board Object Group. | ||
154 | * @param _slots Max number of elements this group can contain. | ||
155 | */ | ||
156 | #define NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE(_eng, _class, _slots) \ | ||
157 | NV_PMU_MAKE_ALIGNED_STRUCT( \ | ||
158 | nv_pmu_##_eng##_##_class##_boardobjgrp_get_status_header, struct); \ | ||
159 | NV_PMU_MAKE_ALIGNED_UNION( \ | ||
160 | nv_pmu_##_eng##_##_class##_boardobj_get_status_union, union); \ | ||
161 | struct nv_pmu_##_eng##_##_class##_boardobj_grp_get_status { \ | ||
162 | union nv_pmu_##_eng##_##_class##_boardobjgrp_get_status_header_aligned \ | ||
163 | hdr; \ | ||
164 | union nv_pmu_##_eng##_##_class##_boardobj_get_status_union_aligned \ | ||
165 | objects[(_slots)]; \ | ||
166 | } | ||
167 | |||
168 | /* | ||
169 | * Macro generating structures for querying dynamic state for classes which | ||
170 | * implement NV_PMU_BOARDOBJGRP_E32 via the NV_PMU_BOARDOBJ_CMD_GRP GET_STATUS | ||
171 | * interface. | ||
172 | * | ||
173 | * @para _eng Name of implementing engine in which this structure is | ||
174 | * found. | ||
175 | * @param _class Class ID of Objects within Board Object Group. | ||
176 | */ | ||
177 | #define NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(_eng, _class) \ | ||
178 | NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE(_eng, _class, \ | ||
179 | CTRL_BOARDOBJGRP_E32_MAX_OBJECTS) | ||
180 | |||
181 | /* | ||
182 | * Macro generating structures for querying dynamic state for classes which | ||
183 | * implement NV_PMU_BOARDOBJGRP_E255 via the NV_PMU_BOARDOBJ_CMD_GRP GET_STATUS | ||
184 | * interface. | ||
185 | * | ||
186 | * @para _eng Name of implementing engine in which this structure is | ||
187 | * found. | ||
188 | * @param _class Class ID of Objects within Board Object Group. | ||
189 | */ | ||
190 | #define NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E255(_eng, _class) \ | ||
191 | NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE(_eng, _class, \ | ||
192 | CTRL_BOARDOBJGRP_E255_MAX_OBJECTS) | ||
193 | |||
194 | |||
195 | #endif /* _GPMUIFBOARDOBJ_H_ */ | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h new file mode 100644 index 00000000..c080197f --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h | |||
@@ -0,0 +1,455 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | #ifndef _GPMUIFCLK_H_ | ||
15 | #define _GPMUIFCLK_H_ | ||
16 | |||
17 | #include "ctrl/ctrlboardobj.h" | ||
18 | #include "ctrl/ctrlvolt.h" | ||
19 | #include "ctrl/ctrlperf.h" | ||
20 | #include "ctrl/ctrlclk.h" | ||
21 | #include "gpmuifboardobj.h" | ||
22 | #include "gpmuifvolt.h" | ||
23 | #include <nvgpu/flcnif_cmn.h> | ||
24 | |||
25 | enum nv_pmu_clk_clkwhich { | ||
26 | clkwhich_mclk = 5, | ||
27 | clkwhich_dispclk = 7, | ||
28 | clkwhich_gpc2clk = 17, | ||
29 | clkwhich_xbar2clk = 19, | ||
30 | clkwhich_sys2clk = 20, | ||
31 | clkwhich_hub2clk = 21, | ||
32 | clkwhich_pwrclk = 24, | ||
33 | clkwhich_nvdclk = 25, | ||
34 | clkwhich_pciegenclk = 31, | ||
35 | }; | ||
36 | |||
37 | /* | ||
38 | * Enumeration of BOARDOBJGRP class IDs within OBJCLK. Used as "classId" | ||
39 | * argument for communications between Kernel and PMU via the various generic | ||
40 | * BOARDOBJGRP interfaces. | ||
41 | */ | ||
42 | #define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_DOMAIN 0x00 | ||
43 | #define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_PROG 0x01 | ||
44 | #define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_VIN_DEVICE 0x02 | ||
45 | #define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_FLL_DEVICE 0x03 | ||
46 | #define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_VF_POINT 0x04 | ||
47 | #define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_FREQ_CONTROLLER 0x05 | ||
48 | |||
49 | /*! | ||
50 | * CLK_DOMAIN BOARDOBJGRP Header structure. Describes global state about the | ||
51 | * CLK_DOMAIN feature. | ||
52 | */ | ||
53 | struct nv_pmu_clk_clk_domain_boardobjgrp_set_header { | ||
54 | struct nv_pmu_boardobjgrp_e32 super; | ||
55 | u32 vbios_domains; | ||
56 | struct ctrl_boardobjgrp_mask_e32 master_domains_mask; | ||
57 | u16 cntr_sampling_periodms; | ||
58 | bool b_override_o_v_o_c; | ||
59 | bool b_debug_mode; | ||
60 | bool b_enforce_vf_monotonicity; | ||
61 | bool b_enforce_vf_smoothening; | ||
62 | u8 volt_rails_max; | ||
63 | struct ctrl_clk_clk_delta deltas; | ||
64 | }; | ||
65 | |||
66 | struct nv_pmu_clk_clk_domain_boardobj_set { | ||
67 | struct nv_pmu_boardobj super; | ||
68 | enum nv_pmu_clk_clkwhich domain; | ||
69 | u32 api_domain; | ||
70 | u8 perf_domain_grp_idx; | ||
71 | }; | ||
72 | |||
73 | struct nv_pmu_clk_clk_domain_3x_boardobj_set { | ||
74 | struct nv_pmu_clk_clk_domain_boardobj_set super; | ||
75 | bool b_noise_aware_capable; | ||
76 | }; | ||
77 | |||
78 | struct nv_pmu_clk_clk_domain_3x_fixed_boardobj_set { | ||
79 | struct nv_pmu_clk_clk_domain_3x_boardobj_set super; | ||
80 | u16 freq_mhz; | ||
81 | }; | ||
82 | |||
83 | struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set { | ||
84 | struct nv_pmu_clk_clk_domain_3x_boardobj_set super; | ||
85 | u8 clk_prog_idx_first; | ||
86 | u8 clk_prog_idx_last; | ||
87 | u8 noise_unaware_ordering_index; | ||
88 | u8 noise_aware_ordering_index; | ||
89 | bool b_force_noise_unaware_ordering; | ||
90 | int factory_offset_khz; | ||
91 | short freq_delta_min_mhz; | ||
92 | short freq_delta_max_mhz; | ||
93 | struct ctrl_clk_clk_delta deltas; | ||
94 | }; | ||
95 | |||
96 | struct nv_pmu_clk_clk_domain_3x_master_boardobj_set { | ||
97 | struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super; | ||
98 | u32 slave_idxs_mask; | ||
99 | }; | ||
100 | |||
101 | struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set { | ||
102 | struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super; | ||
103 | u8 master_idx; | ||
104 | }; | ||
105 | |||
106 | union nv_pmu_clk_clk_domain_boardobj_set_union { | ||
107 | struct nv_pmu_boardobj board_obj; | ||
108 | struct nv_pmu_clk_clk_domain_boardobj_set super; | ||
109 | struct nv_pmu_clk_clk_domain_3x_boardobj_set v3x; | ||
110 | struct nv_pmu_clk_clk_domain_3x_fixed_boardobj_set v3x_fixed; | ||
111 | struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set v3x_prog; | ||
112 | struct nv_pmu_clk_clk_domain_3x_master_boardobj_set v3x_master; | ||
113 | struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set v3x_slave; | ||
114 | }; | ||
115 | |||
116 | NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_domain); | ||
117 | |||
118 | struct nv_pmu_clk_clk_prog_boardobjgrp_set_header { | ||
119 | struct nv_pmu_boardobjgrp_e255 super; | ||
120 | u8 slave_entry_count; | ||
121 | u8 vf_entry_count; | ||
122 | }; | ||
123 | |||
124 | struct nv_pmu_clk_clk_prog_boardobj_set { | ||
125 | struct nv_pmu_boardobj super; | ||
126 | }; | ||
127 | |||
128 | struct nv_pmu_clk_clk_prog_1x_boardobj_set { | ||
129 | struct nv_pmu_clk_clk_prog_boardobj_set super; | ||
130 | u8 source; | ||
131 | u16 freq_max_mhz; | ||
132 | union ctrl_clk_clk_prog_1x_source_data source_data; | ||
133 | }; | ||
134 | |||
135 | struct nv_pmu_clk_clk_prog_1x_master_boardobj_set { | ||
136 | struct nv_pmu_clk_clk_prog_1x_boardobj_set super; | ||
137 | bool b_o_c_o_v_enabled; | ||
138 | struct ctrl_clk_clk_prog_1x_master_vf_entry vf_entries[ | ||
139 | CTRL_CLK_CLK_PROG_1X_MASTER_VF_ENTRY_MAX_ENTRIES]; | ||
140 | union ctrl_clk_clk_prog_1x_master_source_data source_data; | ||
141 | struct ctrl_clk_clk_delta deltas; | ||
142 | }; | ||
143 | |||
144 | struct nv_pmu_clk_clk_prog_1x_master_ratio_boardobj_set { | ||
145 | struct nv_pmu_clk_clk_prog_1x_master_boardobj_set super; | ||
146 | struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry slave_entries[ | ||
147 | CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES]; | ||
148 | }; | ||
149 | |||
150 | struct nv_pmu_clk_clk_prog_1x_master_table_boardobj_set { | ||
151 | struct nv_pmu_clk_clk_prog_1x_master_boardobj_set super; | ||
152 | struct ctrl_clk_clk_prog_1x_master_table_slave_entry | ||
153 | slave_entries[CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES]; | ||
154 | }; | ||
155 | |||
156 | union nv_pmu_clk_clk_prog_boardobj_set_union { | ||
157 | struct nv_pmu_boardobj board_obj; | ||
158 | struct nv_pmu_clk_clk_prog_boardobj_set super; | ||
159 | struct nv_pmu_clk_clk_prog_1x_boardobj_set v1x; | ||
160 | struct nv_pmu_clk_clk_prog_1x_master_boardobj_set v1x_master; | ||
161 | struct nv_pmu_clk_clk_prog_1x_master_ratio_boardobj_set v1x_master_ratio; | ||
162 | struct nv_pmu_clk_clk_prog_1x_master_table_boardobj_set v1x_master_table; | ||
163 | }; | ||
164 | |||
165 | NV_PMU_BOARDOBJ_GRP_SET_MAKE_E255(clk, clk_prog); | ||
166 | |||
167 | struct nv_pmu_clk_lut_device_desc { | ||
168 | u8 vselect_mode; | ||
169 | u16 hysteresis_threshold; | ||
170 | }; | ||
171 | |||
172 | struct nv_pmu_clk_regime_desc { | ||
173 | u8 regime_id; | ||
174 | u16 fixed_freq_regime_limit_mhz; | ||
175 | }; | ||
176 | |||
177 | struct nv_pmu_clk_clk_fll_device_boardobjgrp_set_header { | ||
178 | struct nv_pmu_boardobjgrp_e32 super; | ||
179 | struct ctrl_boardobjgrp_mask_e32 lut_prog_master_mask; | ||
180 | u32 lut_step_size_uv; | ||
181 | u32 lut_min_voltage_uv; | ||
182 | u8 lut_num_entries; | ||
183 | u16 max_min_freq_mhz; | ||
184 | }; | ||
185 | |||
186 | struct nv_pmu_clk_clk_fll_device_boardobj_set { | ||
187 | struct nv_pmu_boardobj super; | ||
188 | u8 id; | ||
189 | u8 mdiv; | ||
190 | u8 vin_idx_logic; | ||
191 | u8 vin_idx_sram; | ||
192 | u8 rail_idx_for_lut; | ||
193 | u16 input_freq_mhz; | ||
194 | u32 clk_domain; | ||
195 | struct nv_pmu_clk_lut_device_desc lut_device; | ||
196 | struct nv_pmu_clk_regime_desc regime_desc; | ||
197 | u8 min_freq_vfe_idx; | ||
198 | u8 freq_ctrl_idx; | ||
199 | struct ctrl_boardobjgrp_mask_e32 lut_prog_broadcast_slave_mask; | ||
200 | }; | ||
201 | |||
202 | union nv_pmu_clk_clk_fll_device_boardobj_set_union { | ||
203 | struct nv_pmu_boardobj board_obj; | ||
204 | struct nv_pmu_clk_clk_fll_device_boardobj_set super; | ||
205 | }; | ||
206 | |||
207 | NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_fll_device); | ||
208 | |||
209 | struct nv_pmu_clk_clk_vin_device_boardobjgrp_set_header { | ||
210 | struct nv_pmu_boardobjgrp_e32 super; | ||
211 | bool b_vin_is_disable_allowed; | ||
212 | }; | ||
213 | |||
214 | struct nv_pmu_clk_clk_vin_device_boardobj_set { | ||
215 | struct nv_pmu_boardobj super; | ||
216 | u8 id; | ||
217 | u8 volt_domain; | ||
218 | u32 slope; | ||
219 | u32 intercept; | ||
220 | u32 flls_shared_mask; | ||
221 | }; | ||
222 | |||
223 | union nv_pmu_clk_clk_vin_device_boardobj_set_union { | ||
224 | struct nv_pmu_boardobj board_obj; | ||
225 | struct nv_pmu_clk_clk_vin_device_boardobj_set super; | ||
226 | }; | ||
227 | |||
228 | NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_vin_device); | ||
229 | |||
230 | struct nv_pmu_clk_clk_vf_point_boardobjgrp_set_header { | ||
231 | struct nv_pmu_boardobjgrp_e255 super; | ||
232 | }; | ||
233 | |||
234 | struct nv_pmu_clk_clk_vf_point_boardobj_set { | ||
235 | struct nv_pmu_boardobj super; | ||
236 | u8 vfe_equ_idx; | ||
237 | u8 volt_rail_idx; | ||
238 | }; | ||
239 | |||
240 | struct nv_pmu_clk_clk_vf_point_freq_boardobj_set { | ||
241 | struct nv_pmu_clk_clk_vf_point_boardobj_set super; | ||
242 | u16 freq_mhz; | ||
243 | int volt_delta_uv; | ||
244 | }; | ||
245 | |||
246 | struct nv_pmu_clk_clk_vf_point_volt_boardobj_set { | ||
247 | struct nv_pmu_clk_clk_vf_point_boardobj_set super; | ||
248 | u32 source_voltage_uv; | ||
249 | int freq_delta_khz; | ||
250 | }; | ||
251 | |||
252 | union nv_pmu_clk_clk_vf_point_boardobj_set_union { | ||
253 | struct nv_pmu_boardobj board_obj; | ||
254 | struct nv_pmu_clk_clk_vf_point_boardobj_set super; | ||
255 | struct nv_pmu_clk_clk_vf_point_freq_boardobj_set freq; | ||
256 | struct nv_pmu_clk_clk_vf_point_volt_boardobj_set volt; | ||
257 | }; | ||
258 | |||
259 | NV_PMU_BOARDOBJ_GRP_SET_MAKE_E255(clk, clk_vf_point); | ||
260 | |||
261 | struct nv_pmu_clk_clk_vf_point_boardobjgrp_get_status_header { | ||
262 | struct nv_pmu_boardobjgrp_e255 super; | ||
263 | }; | ||
264 | |||
265 | struct nv_pmu_clk_clk_vf_point_boardobj_get_status { | ||
266 | struct nv_pmu_boardobj super; | ||
267 | struct ctrl_clk_vf_pair pair; | ||
268 | }; | ||
269 | |||
270 | struct nv_pmu_clk_clk_vf_point_volt_boardobj_get_status { | ||
271 | struct nv_pmu_clk_clk_vf_point_boardobj_get_status super; | ||
272 | u16 vf_gain_value; | ||
273 | }; | ||
274 | |||
275 | union nv_pmu_clk_clk_vf_point_boardobj_get_status_union { | ||
276 | struct nv_pmu_boardobj board_obj; | ||
277 | struct nv_pmu_clk_clk_vf_point_boardobj_get_status super; | ||
278 | struct nv_pmu_clk_clk_vf_point_volt_boardobj_get_status volt; | ||
279 | }; | ||
280 | |||
281 | NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E255(clk, clk_vf_point); | ||
282 | |||
283 | #define NV_PMU_VF_INJECT_MAX_CLOCK_DOMAINS (12) | ||
284 | |||
285 | struct nv_pmu_clk_clk_domain_list { | ||
286 | u8 num_domains; | ||
287 | struct ctrl_clk_clk_domain_list_item clk_domains[ | ||
288 | NV_PMU_VF_INJECT_MAX_CLOCK_DOMAINS]; | ||
289 | }; | ||
290 | |||
291 | struct nv_pmu_clk_vf_change_inject { | ||
292 | u8 flags; | ||
293 | struct nv_pmu_clk_clk_domain_list clk_list; | ||
294 | struct nv_pmu_volt_volt_rail_list volt_list; | ||
295 | }; | ||
296 | |||
297 | #define NV_NV_PMU_CLK_LOAD_FEATURE_VIN (0x00000002) | ||
298 | #define NV_NV_PMU_CLK_LOAD_ACTION_MASK_VIN_HW_CAL_PROGRAM_YES (0x00000001) | ||
299 | |||
300 | struct nv_pmu_clk_load_payload_freq_controllers { | ||
301 | struct ctrl_boardobjgrp_mask_e32 load_mask; | ||
302 | }; | ||
303 | |||
304 | struct nv_pmu_clk_load { | ||
305 | u8 feature; | ||
306 | u32 action_mask; | ||
307 | union { | ||
308 | struct nv_pmu_clk_load_payload_freq_controllers freq_controllers; | ||
309 | } payload; | ||
310 | }; | ||
311 | /* CLK_FREQ_CONTROLLER */ | ||
312 | #define NV_NV_PMU_CLK_LOAD_FEATURE_FREQ_CONTROLLER (0x00000003) | ||
313 | |||
314 | #define NV_NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_CONTROLLER_CALLBACK_NO (0x00000000) | ||
315 | #define NV_NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_CONTROLLER_CALLBACK_YES (0x00000002) | ||
316 | |||
317 | struct nv_pmu_clk_clk_freq_controller_boardobjgrp_set_header { | ||
318 | struct nv_pmu_boardobjgrp_e32 super; | ||
319 | u32 sampling_period_ms; | ||
320 | u8 volt_policy_idx; | ||
321 | }; | ||
322 | |||
323 | struct nv_pmu_clk_clk_freq_controller_boardobj_set { | ||
324 | struct nv_pmu_boardobj super; | ||
325 | u8 controller_id; | ||
326 | u8 parts_freq_mode; | ||
327 | bool bdisable; | ||
328 | u32 clk_domain; | ||
329 | s16 freq_cap_noise_unaware_vmin_above; | ||
330 | s16 freq_cap_noise_unaware_vmin_below; | ||
331 | s16 freq_hyst_pos_mhz; | ||
332 | s16 freq_hyst_neg_mhz; | ||
333 | }; | ||
334 | |||
335 | struct nv_pmu_clk_clk_freq_controller_pi_boardobj_set { | ||
336 | struct nv_pmu_clk_clk_freq_controller_boardobj_set super; | ||
337 | s32 prop_gain; | ||
338 | s32 integ_gain; | ||
339 | s32 integ_decay; | ||
340 | s32 volt_delta_min; | ||
341 | s32 volt_delta_max; | ||
342 | u8 slowdown_pct_min; | ||
343 | bool bpoison; | ||
344 | }; | ||
345 | |||
346 | union nv_pmu_clk_clk_freq_controller_boardobj_set_union { | ||
347 | struct nv_pmu_boardobj board_obj; | ||
348 | struct nv_pmu_clk_clk_freq_controller_boardobj_set super; | ||
349 | struct nv_pmu_clk_clk_freq_controller_pi_boardobj_set pi; | ||
350 | }; | ||
351 | |||
352 | NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_freq_controller); | ||
353 | |||
354 | /* CLK CMD ID definitions. */ | ||
355 | #define NV_PMU_CLK_CMD_ID_BOARDOBJ_GRP_SET (0x00000000) | ||
356 | #define NV_PMU_CLK_CMD_ID_RPC (0x00000001) | ||
357 | #define NV_PMU_CLK_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002) | ||
358 | |||
359 | #define NV_PMU_CLK_RPC_ID_LOAD (0x00000002) | ||
360 | #define NV_PMU_CLK_RPC_ID_CLK_VF_CHANGE_INJECT (0x00000001) | ||
361 | |||
362 | struct nv_pmu_clk_cmd_rpc { | ||
363 | u8 cmd_type; | ||
364 | u8 pad[3]; | ||
365 | struct nv_pmu_allocation request; | ||
366 | }; | ||
367 | |||
368 | #define NV_PMU_CLK_CMD_RPC_ALLOC_OFFSET \ | ||
369 | (offsetof(struct nv_pmu_clk_cmd_rpc, request)) | ||
370 | |||
371 | struct nv_pmu_clk_cmd { | ||
372 | union { | ||
373 | u8 cmd_type; | ||
374 | struct nv_pmu_boardobj_cmd_grp grp_set; | ||
375 | struct nv_pmu_clk_cmd_rpc rpc; | ||
376 | struct nv_pmu_boardobj_cmd_grp grp_get_status; | ||
377 | }; | ||
378 | }; | ||
379 | |||
380 | struct nv_pmu_clk_rpc { | ||
381 | u8 function; | ||
382 | bool b_supported; | ||
383 | bool b_success; | ||
384 | flcn_status flcn_status; | ||
385 | union { | ||
386 | struct nv_pmu_clk_vf_change_inject clk_vf_change_inject; | ||
387 | struct nv_pmu_clk_load clk_load; | ||
388 | } params; | ||
389 | }; | ||
390 | |||
391 | /* CLK MSG ID definitions */ | ||
392 | #define NV_PMU_CLK_MSG_ID_BOARDOBJ_GRP_SET (0x00000000) | ||
393 | #define NV_PMU_CLK_MSG_ID_RPC (0x00000001) | ||
394 | #define NV_PMU_CLK_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002) | ||
395 | |||
396 | struct nv_pmu_clk_msg_rpc { | ||
397 | u8 msg_type; | ||
398 | u8 rsvd[3]; | ||
399 | struct nv_pmu_allocation response; | ||
400 | }; | ||
401 | |||
402 | #define NV_PMU_CLK_MSG_RPC_ALLOC_OFFSET \ | ||
403 | offsetof(struct nv_pmu_clk_msg_rpc, response) | ||
404 | |||
405 | struct nv_pmu_clk_msg { | ||
406 | union { | ||
407 | u8 msg_type; | ||
408 | struct nv_pmu_boardobj_msg_grp grp_set; | ||
409 | struct nv_pmu_clk_msg_rpc rpc; | ||
410 | struct nv_pmu_boardobj_msg_grp grp_get_status; | ||
411 | }; | ||
412 | }; | ||
413 | |||
414 | struct nv_pmu_clk_clk_vin_device_boardobjgrp_get_status_header { | ||
415 | struct nv_pmu_boardobjgrp_e32 super; | ||
416 | }; | ||
417 | |||
418 | struct nv_pmu_clk_clk_vin_device_boardobj_get_status { | ||
419 | struct nv_pmu_boardobj_query super; | ||
420 | u32 actual_voltage_uv; | ||
421 | u32 corrected_voltage_uv; | ||
422 | u8 sampled_code; | ||
423 | u8 override_code; | ||
424 | }; | ||
425 | |||
426 | union nv_pmu_clk_clk_vin_device_boardobj_get_status_union { | ||
427 | struct nv_pmu_boardobj_query board_obj; | ||
428 | struct nv_pmu_clk_clk_vin_device_boardobj_get_status super; | ||
429 | }; | ||
430 | |||
431 | NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(clk, clk_vin_device); | ||
432 | |||
433 | struct nv_pmu_clk_lut_vf_entry { | ||
434 | u32 entry; | ||
435 | }; | ||
436 | |||
437 | struct nv_pmu_clk_clk_fll_device_boardobjgrp_get_status_header { | ||
438 | struct nv_pmu_boardobjgrp_e32 super; | ||
439 | }; | ||
440 | |||
441 | struct nv_pmu_clk_clk_fll_device_boardobj_get_status { | ||
442 | struct nv_pmu_boardobj_query super; | ||
443 | u8 current_regime_id; | ||
444 | u16 min_freq_mhz; | ||
445 | struct nv_pmu_clk_lut_vf_entry lut_vf_curve[NV_UNSIGNED_ROUNDED_DIV(CTRL_CLK_LUT_NUM_ENTRIES, 2)]; | ||
446 | }; | ||
447 | |||
448 | union nv_pmu_clk_clk_fll_device_boardobj_get_status_union { | ||
449 | struct nv_pmu_boardobj_query board_obj; | ||
450 | struct nv_pmu_clk_clk_fll_device_boardobj_get_status super; | ||
451 | }; | ||
452 | |||
453 | NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(clk, clk_fll_device); | ||
454 | |||
455 | #endif /*_GPMUIFCLK_H_*/ | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperf.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperf.h new file mode 100644 index 00000000..9a9a92be --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperf.h | |||
@@ -0,0 +1,117 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | #ifndef _GPMUIFPERF_H_ | ||
14 | #define _GPMUIFPERF_H_ | ||
15 | |||
16 | #include "gpmuifvolt.h" | ||
17 | #include "gpmuifperfvfe.h" | ||
18 | |||
19 | /* | ||
20 | * Enumeration of BOARDOBJGRP class IDs within OBJPERF. Used as "classId" | ||
21 | * argument for communications between Kernel and PMU via the various generic | ||
22 | * BOARDOBJGRP interfaces. | ||
23 | */ | ||
24 | #define NV_PMU_PERF_BOARDOBJGRP_CLASS_ID_VFE_VAR 0x00 | ||
25 | #define NV_PMU_PERF_BOARDOBJGRP_CLASS_ID_VFE_EQU 0x01 | ||
26 | |||
27 | #define NV_PMU_PERF_CMD_ID_RPC (0x00000002) | ||
28 | #define NV_PMU_PERF_CMD_ID_BOARDOBJ_GRP_SET (0x00000003) | ||
29 | #define NV_PMU_PERF_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000004) | ||
30 | |||
31 | struct nv_pmu_perf_cmd_set_object { | ||
32 | u8 cmd_type; | ||
33 | u8 pad[2]; | ||
34 | u8 object_type; | ||
35 | struct nv_pmu_allocation object; | ||
36 | }; | ||
37 | |||
38 | #define NV_PMU_PERF_SET_OBJECT_ALLOC_OFFSET \ | ||
39 | (offsetof(struct nv_pmu_perf_cmd_set_object, object)) | ||
40 | |||
41 | /* RPC IDs */ | ||
42 | #define NV_PMU_PERF_RPC_ID_VFE_LOAD (0x00000001) | ||
43 | |||
44 | /*! | ||
45 | * Command requesting execution of the perf RPC. | ||
46 | */ | ||
47 | struct nv_pmu_perf_cmd_rpc { | ||
48 | u8 cmd_type; | ||
49 | u8 pad[3]; | ||
50 | struct nv_pmu_allocation request; | ||
51 | }; | ||
52 | |||
53 | #define NV_PMU_PERF_CMD_RPC_ALLOC_OFFSET \ | ||
54 | offsetof(struct nv_pmu_perf_cmd_rpc, request) | ||
55 | |||
56 | /*! | ||
57 | * Simply a union of all specific PERF commands. Forms the general packet | ||
58 | * exchanged between the Kernel and PMU when sending and receiving PERF commands | ||
59 | * (respectively). | ||
60 | */ | ||
61 | struct nv_pmu_perf_cmd { | ||
62 | union { | ||
63 | u8 cmd_type; | ||
64 | struct nv_pmu_perf_cmd_set_object set_object; | ||
65 | struct nv_pmu_boardobj_cmd_grp grp_set; | ||
66 | struct nv_pmu_boardobj_cmd_grp grp_get_status; | ||
67 | }; | ||
68 | }; | ||
69 | |||
70 | /*! | ||
71 | * Defines the data structure used to invoke PMU perf RPCs. Same structure is | ||
72 | * used to return the result of the RPC execution. | ||
73 | */ | ||
74 | struct nv_pmu_perf_rpc { | ||
75 | u8 function; | ||
76 | bool b_supported; | ||
77 | bool b_success; | ||
78 | flcn_status flcn_status; | ||
79 | union { | ||
80 | struct nv_pmu_perf_rpc_vfe_equ_eval vfe_equ_eval; | ||
81 | struct nv_pmu_perf_rpc_vfe_load vfe_load; | ||
82 | } params; | ||
83 | }; | ||
84 | |||
85 | |||
86 | /* PERF Message-type Definitions */ | ||
87 | #define NV_PMU_PERF_MSG_ID_RPC (0x00000003) | ||
88 | #define NV_PMU_PERF_MSG_ID_BOARDOBJ_GRP_SET (0x00000004) | ||
89 | #define NV_PMU_PERF_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000006) | ||
90 | #define NV_PMU_PERF_MSG_ID_VFE_CALLBACK (0x00000005) | ||
91 | |||
92 | /*! | ||
93 | * Message carrying the result of the perf RPC execution. | ||
94 | */ | ||
95 | struct nv_pmu_perf_msg_rpc { | ||
96 | u8 msg_type; | ||
97 | u8 rsvd[3]; | ||
98 | struct nv_pmu_allocation response; | ||
99 | }; | ||
100 | |||
101 | #define NV_PMU_PERF_MSG_RPC_ALLOC_OFFSET \ | ||
102 | (offsetof(struct nv_pmu_perf_msg_rpc, response)) | ||
103 | |||
104 | /*! | ||
105 | * Simply a union of all specific PERF messages. Forms the general packet | ||
106 | * exchanged between the Kernel and PMU when sending and receiving PERF messages | ||
107 | * (respectively). | ||
108 | */ | ||
109 | struct nv_pmu_perf_msg { | ||
110 | union { | ||
111 | u8 msg_type; | ||
112 | struct nv_pmu_perf_msg_rpc rpc; | ||
113 | struct nv_pmu_boardobj_msg_grp grp_set; | ||
114 | }; | ||
115 | }; | ||
116 | |||
117 | #endif /* _GPMUIFPERF_H_*/ | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperfvfe.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperfvfe.h new file mode 100644 index 00000000..5f5cafbf --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperfvfe.h | |||
@@ -0,0 +1,220 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | #ifndef _GPMUIFPERFVFE_H_ | ||
14 | #define _GPMUIFPERFVFE_H_ | ||
15 | |||
16 | #include "gpmuifbios.h" | ||
17 | #include "gpmuifboardobj.h" | ||
18 | |||
19 | #define CTRL_PERF_VFE_EQU_QUADRATIC_COEFF_COUNT 0x03 | ||
20 | #define NV_PMU_PERF_RPC_VFE_EQU_EVAL_VAR_COUNT_MAX 2 | ||
21 | #define NV_PMU_PERF_RPC_VFE_EQU_MONITOR_COUNT_MAX 16 | ||
22 | #define NV_PMU_VFE_VAR_SINGLE_SENSED_FUSE_SEGMENTS_MAX 1 | ||
23 | |||
24 | struct nv_pmu_perf_vfe_var_value { | ||
25 | u8 var_type; | ||
26 | u8 reserved[3]; | ||
27 | u32 var_value; | ||
28 | }; | ||
29 | |||
30 | union nv_pmu_perf_vfe_equ_result { | ||
31 | u32 freq_m_hz; | ||
32 | u32 voltu_v; | ||
33 | u32 vf_gain; | ||
34 | int volt_deltau_v; | ||
35 | }; | ||
36 | |||
37 | struct nv_pmu_perf_rpc_vfe_equ_eval { | ||
38 | u8 equ_idx; | ||
39 | u8 var_count; | ||
40 | u8 output_type; | ||
41 | struct nv_pmu_perf_vfe_var_value var_values[ | ||
42 | NV_PMU_PERF_RPC_VFE_EQU_EVAL_VAR_COUNT_MAX]; | ||
43 | union nv_pmu_perf_vfe_equ_result result; | ||
44 | }; | ||
45 | |||
46 | struct nv_pmu_perf_rpc_vfe_load { | ||
47 | bool b_load; | ||
48 | }; | ||
49 | |||
50 | struct nv_pmu_perf_vfe_var_boardobjgrp_get_status_header { | ||
51 | struct nv_pmu_boardobjgrp_e32 super; | ||
52 | }; | ||
53 | |||
54 | struct nv_pmu_perf_vfe_var_get_status_super { | ||
55 | struct nv_pmu_boardobj_query board_obj; | ||
56 | }; | ||
57 | |||
58 | struct nv_pmu_perf_vfe_var_single_sensed_fuse_get_status { | ||
59 | struct nv_pmu_perf_vfe_var_get_status_super super; | ||
60 | u32 fuse_value_integer; | ||
61 | u32 fuse_value_hw_integer; | ||
62 | u8 fuse_version; | ||
63 | bool b_version_check_failed; | ||
64 | }; | ||
65 | |||
66 | union nv_pmu_perf_vfe_var_boardobj_get_status_union { | ||
67 | struct nv_pmu_boardobj_query board_obj; | ||
68 | struct nv_pmu_perf_vfe_var_get_status_super super; | ||
69 | struct nv_pmu_perf_vfe_var_single_sensed_fuse_get_status fuse_status; | ||
70 | }; | ||
71 | |||
72 | NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(perf, vfe_var); | ||
73 | |||
74 | struct nv_pmu_vfe_var { | ||
75 | struct nv_pmu_boardobj super; | ||
76 | u32 out_range_min; | ||
77 | u32 out_range_max; | ||
78 | }; | ||
79 | |||
80 | struct nv_pmu_vfe_var_derived { | ||
81 | struct nv_pmu_vfe_var super; | ||
82 | }; | ||
83 | |||
84 | struct nv_pmu_vfe_var_derived_product { | ||
85 | struct nv_pmu_vfe_var_derived super; | ||
86 | u8 var_idx0; | ||
87 | u8 var_idx1; | ||
88 | }; | ||
89 | |||
90 | struct nv_pmu_vfe_var_derived_sum { | ||
91 | struct nv_pmu_vfe_var_derived super; | ||
92 | u8 var_idx0; | ||
93 | u8 var_idx1; | ||
94 | }; | ||
95 | |||
96 | struct nv_pmu_vfe_var_single { | ||
97 | struct nv_pmu_vfe_var super; | ||
98 | u8 override_type; | ||
99 | u32 override_value; | ||
100 | }; | ||
101 | |||
102 | struct nv_pmu_vfe_var_single_frequency { | ||
103 | struct nv_pmu_vfe_var_single super; | ||
104 | }; | ||
105 | |||
106 | struct nv_pmu_vfe_var_single_sensed { | ||
107 | struct nv_pmu_vfe_var_single super; | ||
108 | }; | ||
109 | |||
110 | struct nv_pmu_vfe_var_single_sensed_fuse_info { | ||
111 | u8 segment_count; | ||
112 | union nv_pmu_bios_vfield_register_segment segments[ | ||
113 | NV_PMU_VFE_VAR_SINGLE_SENSED_FUSE_SEGMENTS_MAX]; | ||
114 | }; | ||
115 | |||
116 | struct nv_pmu_vfe_var_single_sensed_fuse_vfield_info { | ||
117 | struct nv_pmu_vfe_var_single_sensed_fuse_info fuse; | ||
118 | u32 fuse_val_default; | ||
119 | int hw_correction_scale; | ||
120 | int hw_correction_offset; | ||
121 | u8 v_field_id; | ||
122 | }; | ||
123 | |||
124 | struct nv_pmu_vfe_var_single_sensed_fuse_ver_vfield_info { | ||
125 | struct nv_pmu_vfe_var_single_sensed_fuse_info fuse; | ||
126 | u8 ver_expected; | ||
127 | bool b_ver_check; | ||
128 | bool b_use_default_on_ver_check_fail; | ||
129 | u8 v_field_id_ver; | ||
130 | }; | ||
131 | |||
132 | struct nv_pmu_vfe_var_single_sensed_fuse_override_info { | ||
133 | u32 fuse_val_override; | ||
134 | bool b_fuse_regkey_override; | ||
135 | }; | ||
136 | |||
137 | struct nv_pmu_vfe_var_single_sensed_fuse { | ||
138 | struct nv_pmu_vfe_var_single_sensed super; | ||
139 | struct nv_pmu_vfe_var_single_sensed_fuse_override_info override_info; | ||
140 | struct nv_pmu_vfe_var_single_sensed_fuse_vfield_info vfield_info; | ||
141 | struct nv_pmu_vfe_var_single_sensed_fuse_ver_vfield_info vfield_ver_info; | ||
142 | }; | ||
143 | |||
144 | struct nv_pmu_vfe_var_single_sensed_temp { | ||
145 | struct nv_pmu_vfe_var_single_sensed super; | ||
146 | u8 therm_channel_index; | ||
147 | int temp_hysteresis_positive; | ||
148 | int temp_hysteresis_negative; | ||
149 | int temp_default; | ||
150 | }; | ||
151 | |||
152 | struct nv_pmu_vfe_var_single_voltage { | ||
153 | struct nv_pmu_vfe_var_single super; | ||
154 | }; | ||
155 | |||
156 | struct nv_pmu_perf_vfe_var_boardobjgrp_set_header { | ||
157 | struct nv_pmu_boardobjgrp_e32 super; | ||
158 | u8 polling_periodms; | ||
159 | }; | ||
160 | |||
161 | union nv_pmu_perf_vfe_var_boardobj_set_union { | ||
162 | struct nv_pmu_boardobj board_obj; | ||
163 | struct nv_pmu_vfe_var var; | ||
164 | struct nv_pmu_vfe_var_derived var_derived; | ||
165 | struct nv_pmu_vfe_var_derived_product var_derived_product; | ||
166 | struct nv_pmu_vfe_var_derived_sum var_derived_sum; | ||
167 | struct nv_pmu_vfe_var_single var_single; | ||
168 | struct nv_pmu_vfe_var_single_frequency var_single_frequiency; | ||
169 | struct nv_pmu_vfe_var_single_sensed var_single_sensed; | ||
170 | struct nv_pmu_vfe_var_single_sensed_fuse var_single_sensed_fuse; | ||
171 | struct nv_pmu_vfe_var_single_sensed_temp var_single_sensed_temp; | ||
172 | struct nv_pmu_vfe_var_single_voltage var_single_voltage; | ||
173 | }; | ||
174 | |||
175 | NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(perf, vfe_var); | ||
176 | |||
177 | struct nv_pmu_vfe_equ { | ||
178 | struct nv_pmu_boardobj super; | ||
179 | u8 var_idx; | ||
180 | u8 equ_idx_next; | ||
181 | u8 output_type; | ||
182 | u32 out_range_min; | ||
183 | u32 out_range_max; | ||
184 | }; | ||
185 | |||
186 | struct nv_pmu_vfe_equ_compare { | ||
187 | struct nv_pmu_vfe_equ super; | ||
188 | u8 func_id; | ||
189 | u8 equ_idx_true; | ||
190 | u8 equ_idx_false; | ||
191 | u32 criteria; | ||
192 | }; | ||
193 | |||
194 | struct nv_pmu_vfe_equ_minmax { | ||
195 | struct nv_pmu_vfe_equ super; | ||
196 | bool b_max; | ||
197 | u8 equ_idx0; | ||
198 | u8 equ_idx1; | ||
199 | }; | ||
200 | |||
201 | struct nv_pmu_vfe_equ_quadratic { | ||
202 | struct nv_pmu_vfe_equ super; | ||
203 | u32 coeffs[CTRL_PERF_VFE_EQU_QUADRATIC_COEFF_COUNT]; | ||
204 | }; | ||
205 | |||
206 | struct nv_pmu_perf_vfe_equ_boardobjgrp_set_header { | ||
207 | struct nv_pmu_boardobjgrp_e255 super; | ||
208 | }; | ||
209 | |||
210 | union nv_pmu_perf_vfe_equ_boardobj_set_union { | ||
211 | struct nv_pmu_boardobj board_obj; | ||
212 | struct nv_pmu_vfe_equ equ; | ||
213 | struct nv_pmu_vfe_equ_compare equ_comapre; | ||
214 | struct nv_pmu_vfe_equ_minmax equ_minmax; | ||
215 | struct nv_pmu_vfe_equ_quadratic equ_quadratic; | ||
216 | }; | ||
217 | |||
218 | NV_PMU_BOARDOBJ_GRP_SET_MAKE_E255(perf, vfe_equ); | ||
219 | |||
220 | #endif /* _GPMUIFPERFVFE_H_*/ | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifpmgr.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifpmgr.h new file mode 100644 index 00000000..f956ab76 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifpmgr.h | |||
@@ -0,0 +1,434 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | #ifndef _GPMUIFPMGR_H_ | ||
15 | #define _GPMUIFPMGR_H_ | ||
16 | |||
17 | #include "ctrl/ctrlpmgr.h" | ||
18 | #include "gpmuifboardobj.h" | ||
19 | #include <nvgpu/flcnif_cmn.h> | ||
20 | |||
21 | struct nv_pmu_pmgr_i2c_device_desc { | ||
22 | struct nv_pmu_boardobj super; | ||
23 | u8 dcb_index; | ||
24 | u16 i2c_address; | ||
25 | u32 i2c_flags; | ||
26 | u8 i2c_port; | ||
27 | }; | ||
28 | |||
29 | #define NV_PMU_PMGR_I2C_DEVICE_DESC_TABLE_MAX_DEVICES (32) | ||
30 | |||
31 | struct nv_pmu_pmgr_i2c_device_desc_table { | ||
32 | u32 dev_mask; | ||
33 | struct nv_pmu_pmgr_i2c_device_desc | ||
34 | devices[NV_PMU_PMGR_I2C_DEVICE_DESC_TABLE_MAX_DEVICES]; | ||
35 | }; | ||
36 | |||
37 | struct nv_pmu_pmgr_pwr_device_desc { | ||
38 | struct nv_pmu_boardobj super; | ||
39 | u32 power_corr_factor; | ||
40 | }; | ||
41 | |||
42 | #define NV_PMU_PMGR_PWR_DEVICE_INA3221_CH_NUM 0x03 | ||
43 | |||
44 | struct nv_pmu_pmgr_pwr_device_desc_ina3221 { | ||
45 | struct nv_pmu_pmgr_pwr_device_desc super; | ||
46 | u8 i2c_dev_idx; | ||
47 | struct ctrl_pmgr_pwr_device_info_rshunt | ||
48 | r_shuntm_ohm[NV_PMU_PMGR_PWR_DEVICE_INA3221_CH_NUM]; | ||
49 | u16 configuration; | ||
50 | u16 mask_enable; | ||
51 | u32 event_mask; | ||
52 | u16 curr_correct_m; | ||
53 | s16 curr_correct_b; | ||
54 | }; | ||
55 | |||
56 | union nv_pmu_pmgr_pwr_device_desc_union { | ||
57 | struct nv_pmu_boardobj board_obj; | ||
58 | struct nv_pmu_pmgr_pwr_device_desc pwr_dev; | ||
59 | struct nv_pmu_pmgr_pwr_device_desc_ina3221 ina3221; | ||
60 | }; | ||
61 | |||
62 | struct nv_pmu_pmgr_pwr_device_ba_info { | ||
63 | bool b_initialized_and_used; | ||
64 | }; | ||
65 | |||
66 | struct nv_pmu_pmgr_pwr_device_desc_table_header { | ||
67 | struct nv_pmu_boardobjgrp_e32 super; | ||
68 | struct nv_pmu_pmgr_pwr_device_ba_info ba_info; | ||
69 | }; | ||
70 | |||
71 | NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_device_desc_table_header, | ||
72 | sizeof(struct nv_pmu_pmgr_pwr_device_desc_table_header)); | ||
73 | NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_device_desc_union, | ||
74 | sizeof(union nv_pmu_pmgr_pwr_device_desc_union)); | ||
75 | |||
76 | struct nv_pmu_pmgr_pwr_device_desc_table { | ||
77 | union nv_pmu_pmgr_pwr_device_desc_table_header_aligned hdr; | ||
78 | union nv_pmu_pmgr_pwr_device_desc_union_aligned | ||
79 | devices[CTRL_PMGR_PWR_DEVICES_MAX_DEVICES]; | ||
80 | }; | ||
81 | |||
82 | union nv_pmu_pmgr_pwr_device_dmem_size { | ||
83 | union nv_pmu_pmgr_pwr_device_desc_table_header_aligned pwr_device_hdr; | ||
84 | union nv_pmu_pmgr_pwr_device_desc_union_aligned pwr_device; | ||
85 | }; | ||
86 | |||
87 | struct nv_pmu_pmgr_pwr_channel { | ||
88 | struct nv_pmu_boardobj super; | ||
89 | u8 pwr_rail; | ||
90 | u8 ch_idx; | ||
91 | u32 volt_fixedu_v; | ||
92 | u32 pwr_corr_slope; | ||
93 | s32 pwr_corr_offsetm_w; | ||
94 | u32 curr_corr_slope; | ||
95 | s32 curr_corr_offsetm_a; | ||
96 | u32 dependent_ch_mask; | ||
97 | }; | ||
98 | |||
99 | #define NV_PMU_PMGR_PWR_CHANNEL_MAX_CHANNELS 16 | ||
100 | |||
101 | #define NV_PMU_PMGR_PWR_CHANNEL_MAX_CHRELATIONSHIPS 16 | ||
102 | |||
103 | struct nv_pmu_pmgr_pwr_channel_sensor { | ||
104 | struct nv_pmu_pmgr_pwr_channel super; | ||
105 | u8 pwr_dev_idx; | ||
106 | u8 pwr_dev_prov_idx; | ||
107 | }; | ||
108 | |||
109 | struct nv_pmu_pmgr_pwr_channel_pmu_compactible { | ||
110 | u8 pmu_compactible_data[56]; | ||
111 | }; | ||
112 | |||
113 | union nv_pmu_pmgr_pwr_channel_union { | ||
114 | struct nv_pmu_boardobj board_obj; | ||
115 | struct nv_pmu_pmgr_pwr_channel pwr_channel; | ||
116 | struct nv_pmu_pmgr_pwr_channel_sensor sensor; | ||
117 | struct nv_pmu_pmgr_pwr_channel_pmu_compactible pmu_pwr_channel; | ||
118 | }; | ||
119 | |||
120 | #define NV_PMU_PMGR_PWR_MONITOR_TYPE_NO_POLLING 0x02 | ||
121 | |||
122 | struct nv_pmu_pmgr_pwr_monitor_pstate { | ||
123 | u32 hw_channel_mask; | ||
124 | }; | ||
125 | |||
126 | union nv_pmu_pmgr_pwr_monitor_type_specific { | ||
127 | struct nv_pmu_pmgr_pwr_monitor_pstate pstate; | ||
128 | }; | ||
129 | |||
130 | struct nv_pmu_pmgr_pwr_chrelationship_pmu_compactible { | ||
131 | u8 pmu_compactible_data[28]; | ||
132 | }; | ||
133 | |||
134 | union nv_pmu_pmgr_pwr_chrelationship_union { | ||
135 | struct nv_pmu_boardobj board_obj; | ||
136 | struct nv_pmu_pmgr_pwr_chrelationship_pmu_compactible pmu_pwr_chrelationship; | ||
137 | }; | ||
138 | |||
139 | struct nv_pmu_pmgr_pwr_channel_header { | ||
140 | struct nv_pmu_boardobjgrp_e32 super; | ||
141 | u8 type; | ||
142 | union nv_pmu_pmgr_pwr_monitor_type_specific type_specific; | ||
143 | u8 sample_count; | ||
144 | u16 sampling_periodms; | ||
145 | u16 sampling_period_low_powerms; | ||
146 | u32 total_gpu_power_channel_mask; | ||
147 | u32 physical_channel_mask; | ||
148 | }; | ||
149 | |||
150 | struct nv_pmu_pmgr_pwr_chrelationship_header { | ||
151 | struct nv_pmu_boardobjgrp_e32 super; | ||
152 | }; | ||
153 | |||
154 | NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_channel_header, | ||
155 | sizeof(struct nv_pmu_pmgr_pwr_channel_header)); | ||
156 | NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_chrelationship_header, | ||
157 | sizeof(struct nv_pmu_pmgr_pwr_chrelationship_header)); | ||
158 | NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_chrelationship_union, | ||
159 | sizeof(union nv_pmu_pmgr_pwr_chrelationship_union)); | ||
160 | NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_channel_union, | ||
161 | sizeof(union nv_pmu_pmgr_pwr_channel_union)); | ||
162 | |||
163 | struct nv_pmu_pmgr_pwr_channel_desc { | ||
164 | union nv_pmu_pmgr_pwr_channel_header_aligned hdr; | ||
165 | union nv_pmu_pmgr_pwr_channel_union_aligned | ||
166 | channels[NV_PMU_PMGR_PWR_CHANNEL_MAX_CHANNELS]; | ||
167 | }; | ||
168 | |||
169 | struct nv_pmu_pmgr_pwr_chrelationship_desc { | ||
170 | union nv_pmu_pmgr_pwr_chrelationship_header_aligned hdr; | ||
171 | union nv_pmu_pmgr_pwr_chrelationship_union_aligned | ||
172 | ch_rels[NV_PMU_PMGR_PWR_CHANNEL_MAX_CHRELATIONSHIPS]; | ||
173 | }; | ||
174 | |||
175 | union nv_pmu_pmgr_pwr_monitor_dmem_size { | ||
176 | union nv_pmu_pmgr_pwr_channel_header_aligned channel_hdr; | ||
177 | union nv_pmu_pmgr_pwr_channel_union_aligned channel; | ||
178 | union nv_pmu_pmgr_pwr_chrelationship_header_aligned ch_rels_hdr; | ||
179 | union nv_pmu_pmgr_pwr_chrelationship_union_aligned ch_rels; | ||
180 | }; | ||
181 | |||
182 | struct nv_pmu_pmgr_pwr_monitor_pack { | ||
183 | struct nv_pmu_pmgr_pwr_channel_desc channels; | ||
184 | struct nv_pmu_pmgr_pwr_chrelationship_desc ch_rels; | ||
185 | }; | ||
186 | |||
187 | #define NV_PMU_PMGR_PWR_POLICY_MAX_POLICIES 32 | ||
188 | |||
189 | #define NV_PMU_PMGR_PWR_POLICY_MAX_POLICY_RELATIONSHIPS 32 | ||
190 | |||
191 | struct nv_pmu_pmgr_pwr_policy { | ||
192 | struct nv_pmu_boardobj super; | ||
193 | u8 ch_idx; | ||
194 | u8 num_limit_inputs; | ||
195 | u8 limit_unit; | ||
196 | u8 sample_mult; | ||
197 | u32 limit_curr; | ||
198 | u32 limit_min; | ||
199 | u32 limit_max; | ||
200 | struct ctrl_pmgr_pwr_policy_info_integral integral; | ||
201 | enum ctrl_pmgr_pwr_policy_filter_type filter_type; | ||
202 | union ctrl_pmgr_pwr_policy_filter_param filter_param; | ||
203 | }; | ||
204 | |||
205 | struct nv_pmu_pmgr_pwr_policy_hw_threshold { | ||
206 | struct nv_pmu_pmgr_pwr_policy super; | ||
207 | u8 threshold_idx; | ||
208 | u8 low_threshold_idx; | ||
209 | bool b_use_low_threshold; | ||
210 | u16 low_threshold_value; | ||
211 | }; | ||
212 | |||
213 | struct nv_pmu_pmgr_pwr_policy_sw_threshold { | ||
214 | struct nv_pmu_pmgr_pwr_policy super; | ||
215 | u8 threshold_idx; | ||
216 | u8 low_threshold_idx; | ||
217 | bool b_use_low_threshold; | ||
218 | u16 low_threshold_value; | ||
219 | u8 event_id; | ||
220 | }; | ||
221 | |||
222 | struct nv_pmu_pmgr_pwr_policy_pmu_compactible { | ||
223 | u8 pmu_compactible_data[68]; | ||
224 | }; | ||
225 | |||
226 | union nv_pmu_pmgr_pwr_policy_union { | ||
227 | struct nv_pmu_boardobj board_obj; | ||
228 | struct nv_pmu_pmgr_pwr_policy pwr_policy; | ||
229 | struct nv_pmu_pmgr_pwr_policy_hw_threshold hw_threshold; | ||
230 | struct nv_pmu_pmgr_pwr_policy_sw_threshold sw_threshold; | ||
231 | struct nv_pmu_pmgr_pwr_policy_pmu_compactible pmu_pwr_policy; | ||
232 | }; | ||
233 | |||
234 | struct nv_pmu_pmgr_pwr_policy_relationship_pmu_compactible { | ||
235 | u8 pmu_compactible_data[24]; | ||
236 | }; | ||
237 | |||
238 | union nv_pmu_pmgr_pwr_policy_relationship_union { | ||
239 | struct nv_pmu_boardobj board_obj; | ||
240 | struct nv_pmu_pmgr_pwr_policy_relationship_pmu_compactible pmu_pwr_relationship; | ||
241 | }; | ||
242 | |||
243 | struct nv_pmu_pmgr_pwr_violation_pmu_compactible { | ||
244 | u8 pmu_compactible_data[16]; | ||
245 | }; | ||
246 | |||
247 | union nv_pmu_pmgr_pwr_violation_union { | ||
248 | struct nv_pmu_boardobj board_obj; | ||
249 | struct nv_pmu_pmgr_pwr_violation_pmu_compactible violation; | ||
250 | }; | ||
251 | |||
252 | #define NV_PMU_PMGR_PWR_POLICY_DESC_TABLE_VERSION_3X 0x30 | ||
253 | |||
254 | NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_policy_union, | ||
255 | sizeof(union nv_pmu_pmgr_pwr_policy_union)); | ||
256 | NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_policy_relationship_union, | ||
257 | sizeof(union nv_pmu_pmgr_pwr_policy_relationship_union)); | ||
258 | |||
259 | #define NV_PMU_PERF_DOMAIN_GROUP_MAX_GROUPS 2 | ||
260 | |||
261 | struct nv_pmu_perf_domain_group_limits | ||
262 | { | ||
263 | u32 values[NV_PMU_PERF_DOMAIN_GROUP_MAX_GROUPS]; | ||
264 | } ; | ||
265 | |||
266 | #define NV_PMU_PMGR_RESERVED_PWR_POLICY_MASK_COUNT 0x6 | ||
267 | |||
268 | struct nv_pmu_pmgr_pwr_policy_desc_header { | ||
269 | struct nv_pmu_boardobjgrp_e32 super; | ||
270 | u8 version; | ||
271 | bool b_enabled; | ||
272 | u8 low_sampling_mult; | ||
273 | u8 semantic_policy_tbl[CTRL_PMGR_PWR_POLICY_IDX_NUM_INDEXES]; | ||
274 | u16 base_sample_period; | ||
275 | u16 min_client_sample_period; | ||
276 | u32 reserved_pmu_policy_mask[NV_PMU_PMGR_RESERVED_PWR_POLICY_MASK_COUNT]; | ||
277 | struct nv_pmu_perf_domain_group_limits global_ceiling; | ||
278 | }; | ||
279 | |||
280 | NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_policy_desc_header , | ||
281 | sizeof(struct nv_pmu_pmgr_pwr_policy_desc_header )); | ||
282 | |||
283 | struct nv_pmu_pmgr_pwr_policyrel_desc_header { | ||
284 | struct nv_pmu_boardobjgrp_e32 super; | ||
285 | }; | ||
286 | |||
287 | NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_policyrel_desc_header, | ||
288 | sizeof(struct nv_pmu_pmgr_pwr_policyrel_desc_header)); | ||
289 | |||
290 | struct nv_pmu_pmgr_pwr_violation_desc_header { | ||
291 | struct nv_pmu_boardobjgrp_e32 super; | ||
292 | }; | ||
293 | |||
294 | NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_violation_desc_header, | ||
295 | sizeof(struct nv_pmu_pmgr_pwr_violation_desc_header)); | ||
296 | NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_violation_union, | ||
297 | sizeof(union nv_pmu_pmgr_pwr_violation_union)); | ||
298 | |||
299 | struct nv_pmu_pmgr_pwr_policy_desc { | ||
300 | union nv_pmu_pmgr_pwr_policy_desc_header_aligned hdr; | ||
301 | union nv_pmu_pmgr_pwr_policy_union_aligned | ||
302 | policies[NV_PMU_PMGR_PWR_POLICY_MAX_POLICIES]; | ||
303 | }; | ||
304 | |||
305 | struct nv_pmu_pmgr_pwr_policyrel_desc { | ||
306 | union nv_pmu_pmgr_pwr_policyrel_desc_header_aligned hdr; | ||
307 | union nv_pmu_pmgr_pwr_policy_relationship_union_aligned | ||
308 | policy_rels[NV_PMU_PMGR_PWR_POLICY_MAX_POLICY_RELATIONSHIPS]; | ||
309 | }; | ||
310 | |||
311 | struct nv_pmu_pmgr_pwr_violation_desc { | ||
312 | union nv_pmu_pmgr_pwr_violation_desc_header_aligned hdr; | ||
313 | union nv_pmu_pmgr_pwr_violation_union_aligned | ||
314 | violations[CTRL_PMGR_PWR_VIOLATION_MAX]; | ||
315 | }; | ||
316 | |||
317 | union nv_pmu_pmgr_pwr_policy_dmem_size { | ||
318 | union nv_pmu_pmgr_pwr_policy_desc_header_aligned policy_hdr; | ||
319 | union nv_pmu_pmgr_pwr_policy_union_aligned policy; | ||
320 | union nv_pmu_pmgr_pwr_policyrel_desc_header_aligned policy_rels_hdr; | ||
321 | union nv_pmu_pmgr_pwr_policy_relationship_union_aligned policy_rels; | ||
322 | union nv_pmu_pmgr_pwr_violation_desc_header_aligned violation_hdr; | ||
323 | union nv_pmu_pmgr_pwr_violation_union_aligned violation; | ||
324 | }; | ||
325 | |||
326 | struct nv_pmu_pmgr_pwr_policy_pack { | ||
327 | struct nv_pmu_pmgr_pwr_policy_desc policies; | ||
328 | struct nv_pmu_pmgr_pwr_policyrel_desc policy_rels; | ||
329 | struct nv_pmu_pmgr_pwr_violation_desc violations; | ||
330 | }; | ||
331 | |||
332 | #define NV_PMU_PMGR_CMD_ID_SET_OBJECT (0x00000000) | ||
333 | |||
334 | #define NV_PMU_PMGR_MSG_ID_QUERY (0x00000002) | ||
335 | |||
336 | #define NV_PMU_PMGR_CMD_ID_PWR_DEVICES_QUERY (0x00000001) | ||
337 | |||
338 | #define NV_PMU_PMGR_CMD_ID_LOAD (0x00000006) | ||
339 | |||
340 | #define NV_PMU_PMGR_CMD_ID_UNLOAD (0x00000007) | ||
341 | |||
342 | struct nv_pmu_pmgr_cmd_set_object { | ||
343 | u8 cmd_type; | ||
344 | u8 pad[2]; | ||
345 | u8 object_type; | ||
346 | struct nv_pmu_allocation object; | ||
347 | }; | ||
348 | |||
349 | #define NV_PMU_PMGR_SET_OBJECT_ALLOC_OFFSET (0x04) | ||
350 | |||
351 | #define NV_PMU_PMGR_OBJECT_I2C_DEVICE_DESC_TABLE (0x00000000) | ||
352 | |||
353 | #define NV_PMU_PMGR_OBJECT_PWR_DEVICE_DESC_TABLE (0x00000001) | ||
354 | |||
355 | #define NV_PMU_PMGR_OBJECT_PWR_MONITOR (0x00000002) | ||
356 | |||
357 | #define NV_PMU_PMGR_OBJECT_PWR_POLICY (0x00000005) | ||
358 | |||
359 | struct nv_pmu_pmgr_pwr_devices_query_payload { | ||
360 | struct { | ||
361 | u32 powerm_w; | ||
362 | u32 voltageu_v; | ||
363 | u32 currentm_a; | ||
364 | } devices[CTRL_PMGR_PWR_DEVICES_MAX_DEVICES]; | ||
365 | }; | ||
366 | |||
367 | struct nv_pmu_pmgr_cmd_pwr_devices_query { | ||
368 | u8 cmd_type; | ||
369 | u8 pad[3]; | ||
370 | u32 dev_mask; | ||
371 | struct nv_pmu_allocation payload; | ||
372 | }; | ||
373 | |||
374 | #define NV_PMU_PMGR_PWR_DEVICES_QUERY_ALLOC_OFFSET (0x08) | ||
375 | |||
376 | struct nv_pmu_pmgr_cmd_load { | ||
377 | u8 cmd_type; | ||
378 | }; | ||
379 | |||
380 | struct nv_pmu_pmgr_cmd_unload { | ||
381 | u8 cmd_type; | ||
382 | }; | ||
383 | |||
384 | struct nv_pmu_pmgr_cmd { | ||
385 | union { | ||
386 | u8 cmd_type; | ||
387 | struct nv_pmu_pmgr_cmd_set_object set_object; | ||
388 | struct nv_pmu_pmgr_cmd_pwr_devices_query pwr_dev_query; | ||
389 | struct nv_pmu_pmgr_cmd_load load; | ||
390 | struct nv_pmu_pmgr_cmd_unload unload; | ||
391 | }; | ||
392 | }; | ||
393 | |||
394 | #define NV_PMU_PMGR_MSG_ID_SET_OBJECT (0x00000000) | ||
395 | |||
396 | #define NV_PMU_PMGR_MSG_ID_LOAD (0x00000004) | ||
397 | |||
398 | #define NV_PMU_PMGR_MSG_ID_UNLOAD (0x00000005) | ||
399 | |||
400 | struct nv_pmu_pmgr_msg_set_object { | ||
401 | u8 msg_type; | ||
402 | bool b_success; | ||
403 | flcn_status flcnstatus; | ||
404 | u8 object_type; | ||
405 | }; | ||
406 | |||
407 | struct nv_pmu_pmgr_msg_query { | ||
408 | u8 msg_type; | ||
409 | bool b_success; | ||
410 | flcn_status flcnstatus; | ||
411 | u8 cmd_type; | ||
412 | }; | ||
413 | |||
414 | struct nv_pmu_pmgr_msg_load { | ||
415 | u8 msg_type; | ||
416 | bool b_success; | ||
417 | flcn_status flcnstatus; | ||
418 | }; | ||
419 | |||
420 | struct nv_pmu_pmgr_msg_unload { | ||
421 | u8 msg_type; | ||
422 | }; | ||
423 | |||
424 | struct nv_pmu_pmgr_msg { | ||
425 | union { | ||
426 | u8 msg_type; | ||
427 | struct nv_pmu_pmgr_msg_set_object set_object; | ||
428 | struct nv_pmu_pmgr_msg_query query; | ||
429 | struct nv_pmu_pmgr_msg_load load; | ||
430 | struct nv_pmu_pmgr_msg_unload unload; | ||
431 | }; | ||
432 | }; | ||
433 | |||
434 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifseq.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifseq.h new file mode 100644 index 00000000..2927206f --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifseq.h | |||
@@ -0,0 +1,73 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | #ifndef _GPMUIFSEQ_H_ | ||
14 | #define _GPMUIFSEQ_H_ | ||
15 | |||
16 | #include <nvgpu/flcnif_cmn.h> | ||
17 | |||
18 | #define PMU_UNIT_SEQ (0x02) | ||
19 | |||
20 | /*! | ||
21 | * @file gpmuifseq.h | ||
22 | * @brief PMU Command/Message Interfaces - Sequencer | ||
23 | */ | ||
24 | |||
25 | /*! | ||
26 | * Defines the identifiers various high-level types of sequencer commands. | ||
27 | * | ||
28 | * _RUN_SCRIPT @ref NV_PMU_SEQ_CMD_RUN_SCRIPT | ||
29 | */ | ||
30 | enum { | ||
31 | NV_PMU_SEQ_CMD_ID_RUN_SCRIPT = 0, | ||
32 | }; | ||
33 | |||
34 | struct nv_pmu_seq_cmd_run_script { | ||
35 | u8 cmd_type; | ||
36 | u8 pad[3]; | ||
37 | struct pmu_allocation_v3 script_alloc; | ||
38 | struct pmu_allocation_v3 reg_alloc; | ||
39 | }; | ||
40 | |||
41 | #define NV_PMU_SEQ_CMD_ALLOC_OFFSET 4 | ||
42 | |||
43 | #define NV_PMU_SEQ_MSG_ALLOC_OFFSET \ | ||
44 | (NV_PMU_SEQ_CMD_ALLOC_OFFSET + NV_PMU_CMD_ALLOC_SIZE) | ||
45 | |||
46 | struct nv_pmu_seq_cmd { | ||
47 | struct pmu_hdr hdr; | ||
48 | union { | ||
49 | u8 cmd_type; | ||
50 | struct nv_pmu_seq_cmd_run_script run_script; | ||
51 | }; | ||
52 | }; | ||
53 | |||
54 | enum { | ||
55 | NV_PMU_SEQ_MSG_ID_RUN_SCRIPT = 0, | ||
56 | }; | ||
57 | |||
58 | struct nv_pmu_seq_msg_run_script { | ||
59 | u8 msg_type; | ||
60 | u8 error_code; | ||
61 | u16 error_pc; | ||
62 | u32 timeout_stat; | ||
63 | }; | ||
64 | |||
65 | struct nv_pmu_seq_msg { | ||
66 | struct pmu_hdr hdr; | ||
67 | union { | ||
68 | u8 msg_type; | ||
69 | struct nv_pmu_seq_msg_run_script run_script; | ||
70 | }; | ||
71 | }; | ||
72 | |||
73 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuiftherm.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuiftherm.h new file mode 100644 index 00000000..27e811ff --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuiftherm.h | |||
@@ -0,0 +1,93 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | #ifndef _GPMUIFTHERM_H_ | ||
15 | #define _GPMUIFTHERM_H_ | ||
16 | |||
17 | #include <nvgpu/flcnif_cmn.h> | ||
18 | |||
19 | #define NV_PMU_THERM_CMD_ID_RPC 0x00000002 | ||
20 | #define NV_PMU_THERM_MSG_ID_RPC 0x00000002 | ||
21 | #define NV_PMU_THERM_RPC_ID_SLCT 0x00000000 | ||
22 | #define NV_PMU_THERM_RPC_ID_SLCT_EVENT_TEMP_TH_SET 0x00000006 | ||
23 | #define NV_PMU_THERM_EVENT_THERMAL_1 0x00000004 | ||
24 | #define NV_PMU_THERM_CMD_ID_HW_SLOWDOWN_NOTIFICATION 0x00000001 | ||
25 | #define NV_RM_PMU_THERM_HW_SLOWDOWN_NOTIFICATION_REQUEST_ENABLE 0x00000001 | ||
26 | #define NV_PMU_THERM_MSG_ID_EVENT_HW_SLOWDOWN_NOTIFICATION 0x00000001 | ||
27 | |||
28 | struct nv_pmu_therm_rpc_slct_event_temp_th_set { | ||
29 | s32 temp_threshold; | ||
30 | u8 event_id; | ||
31 | flcn_status flcn_stat; | ||
32 | }; | ||
33 | |||
34 | struct nv_pmu_therm_rpc_slct { | ||
35 | u32 mask_enabled; | ||
36 | flcn_status flcn_stat; | ||
37 | }; | ||
38 | |||
39 | struct nv_pmu_therm_rpc { | ||
40 | u8 function; | ||
41 | bool b_supported; | ||
42 | union { | ||
43 | struct nv_pmu_therm_rpc_slct slct; | ||
44 | struct nv_pmu_therm_rpc_slct_event_temp_th_set slct_event_temp_th_set; | ||
45 | } params; | ||
46 | }; | ||
47 | |||
48 | struct nv_pmu_therm_cmd_rpc { | ||
49 | u8 cmd_type; | ||
50 | u8 pad[3]; | ||
51 | struct nv_pmu_allocation request; | ||
52 | }; | ||
53 | |||
54 | struct nv_pmu_therm_cmd_hw_slowdown_notification { | ||
55 | u8 cmd_type; | ||
56 | u8 request; | ||
57 | }; | ||
58 | |||
59 | #define NV_PMU_THERM_CMD_RPC_ALLOC_OFFSET \ | ||
60 | offsetof(struct nv_pmu_therm_cmd_rpc, request) | ||
61 | |||
62 | struct nv_pmu_therm_cmd { | ||
63 | union { | ||
64 | u8 cmd_type; | ||
65 | struct nv_pmu_therm_cmd_rpc rpc; | ||
66 | struct nv_pmu_therm_cmd_hw_slowdown_notification hw_slct_notification; | ||
67 | }; | ||
68 | }; | ||
69 | |||
70 | struct nv_pmu_therm_msg_rpc { | ||
71 | u8 msg_type; | ||
72 | u8 rsvd[3]; | ||
73 | struct nv_pmu_allocation response; | ||
74 | }; | ||
75 | |||
76 | struct nv_pmu_therm_msg_event_hw_slowdown_notification { | ||
77 | u8 msg_type; | ||
78 | u32 mask; | ||
79 | }; | ||
80 | |||
81 | #define NV_PMU_THERM_MSG_RPC_ALLOC_OFFSET \ | ||
82 | offsetof(struct nv_pmu_therm_msg_rpc, response) | ||
83 | |||
84 | struct nv_pmu_therm_msg { | ||
85 | union { | ||
86 | u8 msg_type; | ||
87 | struct nv_pmu_therm_msg_rpc rpc; | ||
88 | struct nv_pmu_therm_msg_event_hw_slowdown_notification hw_slct_msg; | ||
89 | }; | ||
90 | }; | ||
91 | |||
92 | #endif | ||
93 | |||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifthermsensor.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifthermsensor.h new file mode 100644 index 00000000..d240b344 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifthermsensor.h | |||
@@ -0,0 +1,74 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | #ifndef _GPMUIFTHERMSENSOR_H_ | ||
15 | #define _GPMUIFTHERMSENSOR_H_ | ||
16 | |||
17 | #include "ctrl/ctrltherm.h" | ||
18 | #include "gpmuifboardobj.h" | ||
19 | #include <nvgpu/flcnif_cmn.h> | ||
20 | |||
21 | #define NV_PMU_THERM_BOARDOBJGRP_CLASS_ID_THERM_DEVICE 0x00 | ||
22 | #define NV_PMU_THERM_BOARDOBJGRP_CLASS_ID_THERM_CHANNEL 0x01 | ||
23 | |||
24 | #define NV_PMU_THERM_CMD_ID_BOARDOBJ_GRP_SET 0x0000000B | ||
25 | #define NV_PMU_THERM_MSG_ID_BOARDOBJ_GRP_SET 0x00000008 | ||
26 | |||
27 | struct nv_pmu_therm_therm_device_boardobjgrp_set_header { | ||
28 | struct nv_pmu_boardobjgrp_e32 super; | ||
29 | }; | ||
30 | |||
31 | struct nv_pmu_therm_therm_device_boardobj_set { | ||
32 | struct nv_pmu_boardobj super; | ||
33 | }; | ||
34 | |||
35 | struct nv_pmu_therm_therm_device_i2c_boardobj_set { | ||
36 | struct nv_pmu_therm_therm_device_boardobj_set super; | ||
37 | u8 i2c_dev_idx; | ||
38 | }; | ||
39 | |||
40 | union nv_pmu_therm_therm_device_boardobj_set_union { | ||
41 | struct nv_pmu_boardobj board_obj; | ||
42 | struct nv_pmu_therm_therm_device_boardobj_set therm_device; | ||
43 | struct nv_pmu_therm_therm_device_i2c_boardobj_set i2c; | ||
44 | }; | ||
45 | |||
46 | NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(therm, therm_device); | ||
47 | |||
48 | struct nv_pmu_therm_therm_channel_boardobjgrp_set_header { | ||
49 | struct nv_pmu_boardobjgrp_e32 super; | ||
50 | }; | ||
51 | |||
52 | struct nv_pmu_therm_therm_channel_boardobj_set { | ||
53 | struct nv_pmu_boardobj super; | ||
54 | s16 scaling; | ||
55 | s16 offset; | ||
56 | s32 temp_min; | ||
57 | s32 temp_max; | ||
58 | }; | ||
59 | |||
60 | struct nv_pmu_therm_therm_channel_device_boardobj_set { | ||
61 | struct nv_pmu_therm_therm_channel_boardobj_set super; | ||
62 | u8 therm_dev_idx; | ||
63 | u8 therm_dev_prov_idx; | ||
64 | }; | ||
65 | |||
66 | union nv_pmu_therm_therm_channel_boardobj_set_union { | ||
67 | struct nv_pmu_boardobj board_obj; | ||
68 | struct nv_pmu_therm_therm_channel_boardobj_set therm_channel; | ||
69 | struct nv_pmu_therm_therm_channel_device_boardobj_set device; | ||
70 | }; | ||
71 | |||
72 | NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(therm, therm_channel); | ||
73 | |||
74 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h new file mode 100644 index 00000000..7a18caa6 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h | |||
@@ -0,0 +1,326 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | #ifndef _GPMUIFVOLT_H_ | ||
14 | #define _GPMUIFVOLT_H_ | ||
15 | |||
16 | #include "gpmuifboardobj.h" | ||
17 | #include <nvgpu/flcnif_cmn.h> | ||
18 | #include "ctrl/ctrlvolt.h" | ||
19 | |||
20 | #define NV_PMU_VOLT_VALUE_0V_IN_UV (0) | ||
21 | |||
22 | /* ------------- VOLT_RAIL's GRP_SET defines and structures ------------- */ | ||
23 | |||
24 | #define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_RAIL 0x00 | ||
25 | #define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_DEVICE 0x01 | ||
26 | #define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_POLICY 0x02 | ||
27 | |||
28 | |||
29 | struct nv_pmu_volt_volt_rail_boardobjgrp_set_header { | ||
30 | struct nv_pmu_boardobjgrp_e32 super; | ||
31 | }; | ||
32 | |||
33 | struct nv_pmu_volt_volt_rail_boardobj_set { | ||
34 | |||
35 | struct nv_pmu_boardobj super; | ||
36 | u8 rel_limit_vfe_equ_idx; | ||
37 | u8 alt_rel_limit_vfe_equ_idx; | ||
38 | u8 ov_limit_vfe_equ_idx; | ||
39 | u8 vmin_limit_vfe_equ_idx; | ||
40 | u8 volt_margin_limit_vfe_equ_idx; | ||
41 | u8 pwr_equ_idx; | ||
42 | u8 volt_dev_idx_default; | ||
43 | struct ctrl_boardobjgrp_mask_e32 volt_dev_mask; | ||
44 | s32 volt_delta_uv[CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES]; | ||
45 | }; | ||
46 | |||
47 | union nv_pmu_volt_volt_rail_boardobj_set_union { | ||
48 | struct nv_pmu_boardobj board_obj; | ||
49 | struct nv_pmu_volt_volt_rail_boardobj_set super; | ||
50 | }; | ||
51 | |||
52 | NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(volt, volt_rail); | ||
53 | |||
54 | /* ------------ VOLT_DEVICE's GRP_SET defines and structures ------------ */ | ||
55 | |||
56 | struct nv_pmu_volt_volt_device_boardobjgrp_set_header { | ||
57 | struct nv_pmu_boardobjgrp_e32 super; | ||
58 | }; | ||
59 | |||
60 | struct nv_pmu_volt_volt_device_boardobj_set { | ||
61 | struct nv_pmu_boardobj super; | ||
62 | u32 switch_delay_us; | ||
63 | u32 voltage_min_uv; | ||
64 | u32 voltage_max_uv; | ||
65 | u32 volt_step_uv; | ||
66 | }; | ||
67 | |||
68 | struct nv_pmu_volt_volt_device_vid_boardobj_set { | ||
69 | struct nv_pmu_volt_volt_device_boardobj_set super; | ||
70 | s32 voltage_base_uv; | ||
71 | s32 voltage_offset_scale_uv; | ||
72 | u8 gpio_pin[CTRL_VOLT_VOLT_DEV_VID_VSEL_MAX_ENTRIES]; | ||
73 | u8 vsel_mask; | ||
74 | }; | ||
75 | |||
76 | struct nv_pmu_volt_volt_device_pwm_boardobj_set { | ||
77 | struct nv_pmu_volt_volt_device_boardobj_set super; | ||
78 | u32 raw_period; | ||
79 | s32 voltage_base_uv; | ||
80 | s32 voltage_offset_scale_uv; | ||
81 | enum nv_pmu_pmgr_pwm_source pwm_source; | ||
82 | }; | ||
83 | |||
84 | union nv_pmu_volt_volt_device_boardobj_set_union { | ||
85 | struct nv_pmu_boardobj board_obj; | ||
86 | struct nv_pmu_volt_volt_device_boardobj_set super; | ||
87 | struct nv_pmu_volt_volt_device_vid_boardobj_set vid; | ||
88 | struct nv_pmu_volt_volt_device_pwm_boardobj_set pwm; | ||
89 | }; | ||
90 | |||
91 | NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(volt, volt_device); | ||
92 | |||
93 | /* ------------ VOLT_POLICY's GRP_SET defines and structures ------------ */ | ||
94 | struct nv_pmu_volt_volt_policy_boardobjgrp_set_header { | ||
95 | |||
96 | struct nv_pmu_boardobjgrp_e32 super; | ||
97 | }; | ||
98 | |||
99 | struct nv_pmu_volt_volt_policy_boardobj_set { | ||
100 | struct nv_pmu_boardobj super; | ||
101 | }; | ||
102 | struct nv_pmu_volt_volt_policy_sr_boardobj_set { | ||
103 | struct nv_pmu_volt_volt_policy_boardobj_set super; | ||
104 | u8 rail_idx; | ||
105 | }; | ||
106 | |||
107 | struct nv_pmu_volt_volt_policy_splt_r_boardobj_set { | ||
108 | struct nv_pmu_volt_volt_policy_boardobj_set super; | ||
109 | u8 rail_idx_master; | ||
110 | u8 rail_idx_slave; | ||
111 | u8 delta_min_vfe_equ_idx; | ||
112 | u8 delta_max_vfe_equ_idx; | ||
113 | s32 offset_delta_min_uv; | ||
114 | s32 offset_delta_max_uv; | ||
115 | }; | ||
116 | |||
117 | struct nv_pmu_volt_volt_policy_srms_boardobj_set { | ||
118 | struct nv_pmu_volt_volt_policy_splt_r_boardobj_set super; | ||
119 | u16 inter_switch_delayus; | ||
120 | }; | ||
121 | |||
122 | /* sr - > single_rail */ | ||
123 | struct nv_pmu_volt_volt_policy_srss_boardobj_set { | ||
124 | struct nv_pmu_volt_volt_policy_splt_r_boardobj_set super; | ||
125 | }; | ||
126 | |||
127 | union nv_pmu_volt_volt_policy_boardobj_set_union { | ||
128 | struct nv_pmu_boardobj board_obj; | ||
129 | struct nv_pmu_volt_volt_policy_boardobj_set super; | ||
130 | struct nv_pmu_volt_volt_policy_sr_boardobj_set single_rail; | ||
131 | struct nv_pmu_volt_volt_policy_splt_r_boardobj_set split_rail; | ||
132 | struct nv_pmu_volt_volt_policy_srms_boardobj_set | ||
133 | split_rail_m_s; | ||
134 | struct nv_pmu_volt_volt_policy_srss_boardobj_set | ||
135 | split_rail_s_s; | ||
136 | }; | ||
137 | |||
138 | NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(volt, volt_policy); | ||
139 | |||
140 | /* ----------- VOLT_RAIL's GRP_GET_STATUS defines and structures ----------- */ | ||
141 | struct nv_pmu_volt_volt_rail_boardobjgrp_get_status_header { | ||
142 | struct nv_pmu_boardobjgrp_e32 super; | ||
143 | }; | ||
144 | |||
145 | struct nv_pmu_volt_volt_rail_boardobj_get_status { | ||
146 | struct nv_pmu_boardobj_query super; | ||
147 | u32 curr_volt_defaultu_v; | ||
148 | u32 rel_limitu_v; | ||
149 | u32 alt_rel_limitu_v; | ||
150 | u32 ov_limitu_v; | ||
151 | u32 max_limitu_v; | ||
152 | u32 vmin_limitu_v; | ||
153 | s32 volt_margin_limitu_v; | ||
154 | u32 rsvd; | ||
155 | }; | ||
156 | |||
157 | union nv_pmu_volt_volt_rail_boardobj_get_status_union { | ||
158 | struct nv_pmu_boardobj_query board_obj; | ||
159 | struct nv_pmu_volt_volt_rail_boardobj_get_status super; | ||
160 | }; | ||
161 | |||
162 | NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(volt, volt_rail); | ||
163 | |||
164 | /* ---------- VOLT_DEVICE's GRP_GET_STATUS defines and structures ---------- */ | ||
165 | struct nv_pmu_volt_volt_device_boardobjgrp_get_status_header { | ||
166 | struct nv_pmu_boardobjgrp_e32 super; | ||
167 | }; | ||
168 | |||
169 | struct nv_pmu_volt_volt_device_boardobj_get_status { | ||
170 | struct nv_pmu_boardobj_query super; | ||
171 | }; | ||
172 | |||
173 | union nv_pmu_volt_volt_device_boardobj_get_status_union { | ||
174 | struct nv_pmu_boardobj_query board_obj; | ||
175 | struct nv_pmu_volt_volt_device_boardobj_get_status super; | ||
176 | }; | ||
177 | |||
178 | NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(volt, volt_device); | ||
179 | |||
180 | /* ---------- VOLT_POLICY's GRP_GET_STATUS defines and structures ---------- */ | ||
181 | struct nv_pmu_volt_volt_policy_boardobjgrp_get_status_header { | ||
182 | struct nv_pmu_boardobjgrp_e32 super; | ||
183 | }; | ||
184 | |||
185 | struct nv_pmu_volt_volt_policy_boardobj_get_status { | ||
186 | struct nv_pmu_boardobj_query super; | ||
187 | u32 offset_volt_requ_v; | ||
188 | u32 offset_volt_curru_v; | ||
189 | }; | ||
190 | |||
191 | struct nv_pmu_volt_volt_policy_sr_boardobj_get_status { | ||
192 | struct nv_pmu_volt_volt_policy_boardobj_get_status super; | ||
193 | u32 curr_voltu_v; | ||
194 | }; | ||
195 | |||
196 | struct nv_pmu_volt_volt_policy_splt_r_boardobj_get_status { | ||
197 | struct nv_pmu_volt_volt_policy_boardobj_get_status super; | ||
198 | s32 delta_minu_v; | ||
199 | s32 delta_maxu_v; | ||
200 | s32 orig_delta_minu_v; | ||
201 | s32 orig_delta_maxu_v; | ||
202 | u32 curr_volt_masteru_v; | ||
203 | u32 curr_volt_slaveu_v; | ||
204 | bool b_violation; | ||
205 | }; | ||
206 | |||
207 | /* srms -> split_rail_multi_step */ | ||
208 | struct nv_pmu_volt_volt_policy_srms_boardobj_get_status { | ||
209 | struct nv_pmu_volt_volt_policy_splt_r_boardobj_get_status super; | ||
210 | }; | ||
211 | |||
212 | /* srss -> split_rail_single_step */ | ||
213 | struct nv_pmu_volt_volt_policy_srss_boardobj_get_status { | ||
214 | struct nv_pmu_volt_volt_policy_splt_r_boardobj_get_status super; | ||
215 | }; | ||
216 | |||
217 | union nv_pmu_volt_volt_policy_boardobj_get_status_union { | ||
218 | struct nv_pmu_boardobj_query board_obj; | ||
219 | struct nv_pmu_volt_volt_policy_boardobj_get_status super; | ||
220 | struct nv_pmu_volt_volt_policy_sr_boardobj_get_status single_rail; | ||
221 | struct nv_pmu_volt_volt_policy_splt_r_boardobj_get_status split_rail; | ||
222 | struct nv_pmu_volt_volt_policy_srms_boardobj_get_status | ||
223 | split_rail_m_s; | ||
224 | struct nv_pmu_volt_volt_policy_srss_boardobj_get_status | ||
225 | split_rail_s_s; | ||
226 | }; | ||
227 | |||
228 | NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(volt, volt_policy); | ||
229 | |||
230 | struct nv_pmu_volt_policy_voltage_data { | ||
231 | u8 policy_idx; | ||
232 | struct ctrl_perf_volt_rail_list | ||
233 | rail_list; | ||
234 | }; | ||
235 | |||
236 | struct nv_pmu_volt_rail_get_voltage { | ||
237 | u8 rail_idx; | ||
238 | u32 voltage_uv; | ||
239 | }; | ||
240 | |||
241 | struct nv_pmu_volt_volt_rail_set_noise_unaware_vmin { | ||
242 | u8 num_rails; | ||
243 | struct ctrl_volt_volt_rail_list | ||
244 | rail_list; | ||
245 | }; | ||
246 | |||
247 | #define NV_PMU_VOLT_CMD_ID_BOARDOBJ_GRP_SET (0x00000000) | ||
248 | #define NV_PMU_VOLT_CMD_ID_RPC (0x00000001) | ||
249 | #define NV_PMU_VOLT_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002) | ||
250 | #define NV_PMU_VOLT_RPC_ID_VOLT_RAIL_SET_NOISE_UNAWARE_VMIN (0x00000004) | ||
251 | |||
252 | /*! | ||
253 | * PMU VOLT RPC calls. | ||
254 | */ | ||
255 | #define NV_PMU_VOLT_RPC_ID_LOAD (0x00000000) | ||
256 | #define NV_PMU_VOLT_RPC_ID_VOLT_POLICY_SET_VOLTAGE (0x00000002) | ||
257 | #define NV_PMU_VOLT_RPC_ID_VOLT_RAIL_GET_VOLTAGE (0x00000003) | ||
258 | |||
259 | struct nv_pmu_volt_cmd_rpc { | ||
260 | u8 cmd_type; | ||
261 | u8 pad[3]; | ||
262 | struct nv_pmu_allocation request; | ||
263 | }; | ||
264 | |||
265 | #define NV_PMU_VOLT_CMD_RPC_ALLOC_OFFSET \ | ||
266 | offsetof(struct nv_pmu_volt_cmd_rpc, request) | ||
267 | |||
268 | struct nv_pmu_volt_cmd { | ||
269 | union { | ||
270 | u8 cmd_type; | ||
271 | struct nv_pmu_boardobj_cmd_grp grp_set; | ||
272 | struct nv_pmu_volt_cmd_rpc rpc; | ||
273 | struct nv_pmu_boardobj_cmd_grp grp_get_status; | ||
274 | }; | ||
275 | }; | ||
276 | |||
277 | struct nv_pmu_volt_rpc { | ||
278 | u8 function; | ||
279 | bool b_supported; | ||
280 | bool b_success; | ||
281 | flcn_status flcn_status; | ||
282 | union { | ||
283 | struct nv_pmu_volt_policy_voltage_data volt_policy_voltage_data; | ||
284 | struct nv_pmu_volt_rail_get_voltage volt_rail_get_voltage; | ||
285 | struct nv_pmu_volt_volt_rail_set_noise_unaware_vmin | ||
286 | volt_rail_set_noise_unaware_vmin; | ||
287 | } params; | ||
288 | }; | ||
289 | |||
290 | /*! | ||
291 | * VOLT MSG ID definitions | ||
292 | */ | ||
293 | #define NV_PMU_VOLT_MSG_ID_BOARDOBJ_GRP_SET (0x00000000) | ||
294 | #define NV_PMU_VOLT_MSG_ID_RPC (0x00000001) | ||
295 | #define NV_PMU_VOLT_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002) | ||
296 | |||
297 | /*! | ||
298 | * Message carrying the result of the VOLT RPC execution. | ||
299 | */ | ||
300 | struct nv_pmu_volt_msg_rpc { | ||
301 | u8 msg_type; | ||
302 | u8 rsvd[3]; | ||
303 | struct nv_pmu_allocation response; | ||
304 | }; | ||
305 | |||
306 | #define NV_PMU_VOLT_MSG_RPC_ALLOC_OFFSET \ | ||
307 | offsetof(struct nv_pmu_volt_msg_rpc, response) | ||
308 | |||
309 | struct nv_pmu_volt_msg { | ||
310 | union { | ||
311 | u8 msg_type; | ||
312 | struct nv_pmu_boardobj_msg_grp grp_set; | ||
313 | struct nv_pmu_volt_msg_rpc rpc; | ||
314 | struct nv_pmu_boardobj_msg_grp grp_get_status; | ||
315 | }; | ||
316 | }; | ||
317 | |||
318 | #define NV_PMU_VF_INJECT_MAX_VOLT_RAILS (2) | ||
319 | |||
320 | struct nv_pmu_volt_volt_rail_list { | ||
321 | u8 num_rails; | ||
322 | struct ctrl_perf_volt_rail_list_item | ||
323 | rails[NV_PMU_VF_INJECT_MAX_VOLT_RAILS]; | ||
324 | }; | ||
325 | |||
326 | #endif /* _GPMUIFVOLT_H_*/ | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/nvgpu_gpmu_cmdif.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/nvgpu_gpmu_cmdif.h new file mode 100644 index 00000000..01cd2743 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/nvgpu_gpmu_cmdif.h | |||
@@ -0,0 +1,89 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | #ifndef _NVGPUGPMUCMDIF_H_ | ||
14 | #define _NVGPUGPMUCMDIF_H_ | ||
15 | |||
16 | #include <nvgpu/flcnif_cmn.h> | ||
17 | #include "gpmuif_cmn.h" | ||
18 | #include "gpmuif_pmu.h" | ||
19 | #include "gpmuif_ap.h" | ||
20 | #include "gpmuif_pg.h" | ||
21 | #include "gpmuif_perfmon.h" | ||
22 | #include "gpmuif_acr.h" | ||
23 | #include "gpmuifboardobj.h" | ||
24 | #include "gpmuifclk.h" | ||
25 | #include "gpmuifperf.h" | ||
26 | #include "gpmuifperfvfe.h" | ||
27 | #include "gpmuifpmgr.h" | ||
28 | #include "gpmuifvolt.h" | ||
29 | #include "gpmuiftherm.h" | ||
30 | #include "gpmuifthermsensor.h" | ||
31 | #include "gpmuifseq.h" | ||
32 | |||
33 | struct pmu_cmd { | ||
34 | struct pmu_hdr hdr; | ||
35 | union { | ||
36 | struct pmu_perfmon_cmd perfmon; | ||
37 | struct pmu_pg_cmd pg; | ||
38 | struct pmu_zbc_cmd zbc; | ||
39 | struct pmu_acr_cmd acr; | ||
40 | struct nv_pmu_boardobj_cmd boardobj; | ||
41 | struct nv_pmu_perf_cmd perf; | ||
42 | struct nv_pmu_volt_cmd volt; | ||
43 | struct nv_pmu_clk_cmd clk; | ||
44 | struct nv_pmu_pmgr_cmd pmgr; | ||
45 | struct nv_pmu_therm_cmd therm; | ||
46 | } cmd; | ||
47 | }; | ||
48 | |||
49 | struct pmu_msg { | ||
50 | struct pmu_hdr hdr; | ||
51 | union { | ||
52 | struct pmu_init_msg init; | ||
53 | struct pmu_perfmon_msg perfmon; | ||
54 | struct pmu_pg_msg pg; | ||
55 | struct pmu_rc_msg rc; | ||
56 | struct pmu_acr_msg acr; | ||
57 | struct nv_pmu_boardobj_msg boardobj; | ||
58 | struct nv_pmu_perf_msg perf; | ||
59 | struct nv_pmu_volt_msg volt; | ||
60 | struct nv_pmu_clk_msg clk; | ||
61 | struct nv_pmu_pmgr_msg pmgr; | ||
62 | struct nv_pmu_therm_msg therm; | ||
63 | } msg; | ||
64 | }; | ||
65 | |||
66 | #define PMU_UNIT_REWIND (0x00) | ||
67 | #define PMU_UNIT_PG (0x03) | ||
68 | #define PMU_UNIT_INIT (0x07) | ||
69 | #define PMU_UNIT_ACR (0x0A) | ||
70 | #define PMU_UNIT_PERFMON_T18X (0x11) | ||
71 | #define PMU_UNIT_PERFMON (0x12) | ||
72 | #define PMU_UNIT_PERF (0x13) | ||
73 | #define PMU_UNIT_RC (0x1F) | ||
74 | #define PMU_UNIT_FECS_MEM_OVERRIDE (0x1E) | ||
75 | #define PMU_UNIT_CLK (0x0D) | ||
76 | #define PMU_UNIT_THERM (0x14) | ||
77 | #define PMU_UNIT_PMGR (0x18) | ||
78 | #define PMU_UNIT_VOLT (0x0E) | ||
79 | |||
80 | #define PMU_UNIT_END (0x23) | ||
81 | |||
82 | #define PMU_UNIT_TEST_START (0xFE) | ||
83 | #define PMU_UNIT_END_SIM (0xFF) | ||
84 | #define PMU_UNIT_TEST_END (0xFF) | ||
85 | |||
86 | #define PMU_UNIT_ID_IS_VALID(id) \ | ||
87 | (((id) < PMU_UNIT_END) || ((id) >= PMU_UNIT_TEST_START)) | ||
88 | |||
89 | #endif /* _NVGPUGPMUCMDIF_H_*/ | ||