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authorAlex Waterman <alexw@nvidia.com>2017-08-11 16:35:24 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-08-14 14:18:31 -0400
commit36f02cf49729b32aa241cb9f1f235749da681dd1 (patch)
treeac2569ec2c828489a56aedcf9c85cadcbc0dee62 /drivers/gpu/nvgpu/include
parent4412728b9606a2e2506961ed6e444a344af7ca29 (diff)
gpu: nvgpu: Add struct gk20a ptr to FUSE APIs
Add a pointer to struct gk20a to the FUSE APIs. This helps QNX builds avoid any static data definitions. Also this change plumbs struct gk20a in some of the Linux clk code and fixes a few minor style nits. Change-Id: I27dfb2c4e9a352f784d6cead150460d8e9e808d3 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1537611 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/fuse.h16
1 files changed, 9 insertions, 7 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/fuse.h b/drivers/gpu/nvgpu/include/nvgpu/fuse.h
index 3650fd58..c10ece1d 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/fuse.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/fuse.h
@@ -13,13 +13,15 @@
13#ifndef __NVGPU_FUSE_H__ 13#ifndef __NVGPU_FUSE_H__
14#define __NVGPU_FUSE_H__ 14#define __NVGPU_FUSE_H__
15 15
16int nvgpu_tegra_get_gpu_speedo_id(void); 16struct gk20a;
17 17
18void nvgpu_tegra_fuse_write_bypass(u32 val); 18int nvgpu_tegra_get_gpu_speedo_id(struct gk20a *g);
19void nvgpu_tegra_fuse_write_access_sw(u32 val); 19
20void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(u32 val); 20void nvgpu_tegra_fuse_write_bypass(struct gk20a *g, u32 val);
21void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(u32 val); 21void nvgpu_tegra_fuse_write_access_sw(struct gk20a *g, u32 val);
22int nvgpu_tegra_fuse_read_gcplex_config_fuse(u32 *val); 22void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(struct gk20a *g, u32 val);
23int nvgpu_tegra_fuse_read_reserved_calib(u32 *val); 23void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(struct gk20a *g, u32 val);
24int nvgpu_tegra_fuse_read_gcplex_config_fuse(struct gk20a *g, u32 *val);
25int nvgpu_tegra_fuse_read_reserved_calib(struct gk20a *g, u32 *val);
24 26
25#endif 27#endif