gpu: nvgpu: Add pd_max_batches sysfs node for gp10b

Add a new sysfs node pd_max_batches for setting max batches value in
NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_BATCHES register which controls
max number of batches per alpha-beta transition stored in PD.

Bug 1927124

Change-Id: I2817f2d70dab348d8b0b8ba19bf1e9b9d23ca907
Signed-off-by: Sandeep Shinde <sashinde@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1544104
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
(cherry picked from commit aa4daddda23aa44a84464200f497eac802a8e6ce)
Reviewed-on: https://git-master.nvidia.com/r/1543355
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit

1 files changed, 4 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h
index fe902cbb..e56923c6 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h
@@ -1662,6 +1662,10 @@ static inline u32 gr_pd_ab_dist_cfg1_r(void)
 {
         return 0x004064c4;
 }
+static inline u32 gr_pd_ab_dist_cfg1_max_batches_f(u32 v)
+{
+        return (v & 0xffff) << 0;
+}
 static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void)
 {
         return 0xffff;