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author | Aparna Das <aparnad@nvidia.com> | 2018-04-05 22:20:40 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-04-23 01:13:29 -0400 |
commit | 31024f85ebda64b0fed0e487f4730cfdccf9ee8e (patch) | |
tree | 0bc83fb41758039c932bc54b373ab3725d88dbc3 /drivers/gpu/nvgpu/include | |
parent | d0e4dfd6efd651abc431aba9cfae5907638f8172 (diff) |
nvgpu: vgpu: add support to query rop_l2 en masks
Fetch ROP_L2 enable masks in addition to other parameters
when guest sends command to query constants.
Bug 200401223
Change-Id: Ie386f24caaf7acd1155fc3f2a5e8c1f27016970a
Signed-off-by: Aparna Das <aparnad@nvidia.com>
(cherry picked from commit a08bb08fb9fff40138d26e5e9bfa21267ca6b6af)
Reviewed-on: https://git-master.nvidia.com/r/1694911
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h index ba7d2ba2..f34fc5e7 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h | |||
@@ -455,6 +455,7 @@ struct tegra_vgpu_engines_info { | |||
455 | 455 | ||
456 | #define TEGRA_VGPU_MAX_GPC_COUNT 16 | 456 | #define TEGRA_VGPU_MAX_GPC_COUNT 16 |
457 | #define TEGRA_VGPU_MAX_TPC_COUNT_PER_GPC 16 | 457 | #define TEGRA_VGPU_MAX_TPC_COUNT_PER_GPC 16 |
458 | #define TEGRA_VGPU_L2_EN_MASK 32 | ||
458 | 459 | ||
459 | struct tegra_vgpu_constants_params { | 460 | struct tegra_vgpu_constants_params { |
460 | u32 arch; | 461 | u32 arch; |
@@ -494,6 +495,7 @@ struct tegra_vgpu_constants_params { | |||
494 | u32 num_pce; | 495 | u32 num_pce; |
495 | u32 sm_per_tpc; | 496 | u32 sm_per_tpc; |
496 | u32 max_subctx_count; | 497 | u32 max_subctx_count; |
498 | u32 l2_en_mask[TEGRA_VGPU_L2_EN_MASK]; | ||
497 | }; | 499 | }; |
498 | 500 | ||
499 | struct tegra_vgpu_channel_cyclestats_snapshot_params { | 501 | struct tegra_vgpu_channel_cyclestats_snapshot_params { |