gpu: nvgpu: common: fix MISRA Rule 10.4

MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.

Adding "U" at the end of the integer literals to have same type of
operands when an arithmetic operation is performed.

This fix violations where an arithmetic operation is performed on
signed and unsigned int types.

In balloc_get_order_list() the argument "int order" has been changed to
a u64 because all callers of this function pass a u64 argument.

JIRA NVGPU-992

Change-Id: Ie2964f9f1dfb2865a9bd6e6cdd65e7cda6c1f638
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1784419
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

5 files changed, 18 insertions, 18 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/allocator.h b/drivers/gpu/nvgpu/include/nvgpu/allocator.h
index a38e8d51..698aafb3 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/allocator.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/allocator.h
@@ -186,11 +186,11 @@ nvgpu_alloc_carveout_from_co_entry(struct nvgpu_list_node *node)
  *     pointing to the allocation base (requires GPU_ALLOC_FORCE_CONTIG to be
  *     set as well).
  */
-#define GPU_ALLOC_GVA_SPACE             0x1
-#define GPU_ALLOC_NO_ALLOC_PAGE         0x2
-#define GPU_ALLOC_4K_VIDMEM_PAGES       0x4
-#define GPU_ALLOC_FORCE_CONTIG          0x8
-#define GPU_ALLOC_NO_SCATTER_GATHER     0x10
+#define GPU_ALLOC_GVA_SPACE             BIT(0)
+#define GPU_ALLOC_NO_ALLOC_PAGE         BIT(1)
+#define GPU_ALLOC_4K_VIDMEM_PAGES       BIT(2)
+#define GPU_ALLOC_FORCE_CONTIG          BIT(3)
+#define GPU_ALLOC_NO_SCATTER_GATHER     BIT(4)
 
 static inline void alloc_lock(struct nvgpu_allocator *a)
 {
@@ -236,7 +236,7 @@ int nvgpu_lockless_allocator_init(struct gk20a *g, struct nvgpu_allocator *na,
                                   const char *name, u64 base, u64 length,
                                   u64 struct_size, u64 flags);
 
-#define GPU_BALLOC_MAX_ORDER            31
+#define GPU_BALLOC_MAX_ORDER            31U
 
 /*
  * Allocator APIs.
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gmmu.h b/drivers/gpu/nvgpu/include/nvgpu/gmmu.h
index a83b0dd8..e58f5498 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gmmu.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gmmu.h
@@ -54,9 +54,9 @@ enum gk20a_mem_rw_flag {
  * structure is of course depending on this. The MIN_SHIFT define is the right
  * number of bits to shift to determine which list to use in the array of lists.
  */
-#define NVGPU_PD_CACHE_MIN              256
-#define NVGPU_PD_CACHE_MIN_SHIFT        9
-#define NVGPU_PD_CACHE_COUNT            4
+#define NVGPU_PD_CACHE_MIN              256U
+#define NVGPU_PD_CACHE_MIN_SHIFT        9U
+#define NVGPU_PD_CACHE_COUNT            4U
 
 struct nvgpu_pd_mem_entry {
         struct nvgpu_mem                mem;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/types.h b/drivers/gpu/nvgpu/include/nvgpu/posix/types.h
index 4b525923..97686eec 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/posix/types.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/posix/types.h
@@ -72,7 +72,7 @@ typedef long long		s64;
         })
 #define min3(a, b, c)                   min(min(a, b), c)
 
-#define PAGE_SIZE       4096
+#define PAGE_SIZE       4096U
 
 #define ARRAY_SIZE(array)                       \
         (sizeof(array) / sizeof((array)[0]))
diff --git a/drivers/gpu/nvgpu/include/nvgpu/vm.h b/drivers/gpu/nvgpu/include/nvgpu/vm.h
index ad8c7cca..b47d4ee0 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/vm.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/vm.h
@@ -207,12 +207,12 @@ struct vm_gk20a {
 /*
  * Mapping flags.
  */
-#define NVGPU_VM_MAP_FIXED_OFFSET                       (1 << 0)
-#define NVGPU_VM_MAP_CACHEABLE                          (1 << 1)
-#define NVGPU_VM_MAP_IO_COHERENT                        (1 << 2)
-#define NVGPU_VM_MAP_UNMAPPED_PTE                       (1 << 3)
-#define NVGPU_VM_MAP_DIRECT_KIND_CTRL                   (1 << 4)
-#define NVGPU_VM_MAP_L3_ALLOC                           (1 << 5)
+#define NVGPU_VM_MAP_FIXED_OFFSET                       BIT32(0)
+#define NVGPU_VM_MAP_CACHEABLE                          BIT32(1)
+#define NVGPU_VM_MAP_IO_COHERENT                        BIT32(2)
+#define NVGPU_VM_MAP_UNMAPPED_PTE                       BIT32(3)
+#define NVGPU_VM_MAP_DIRECT_KIND_CTRL                   BIT32(4)
+#define NVGPU_VM_MAP_L3_ALLOC                           BIT32(5)
 
 #define NVGPU_KIND_INVALID                              -1
 
diff --git a/drivers/gpu/nvgpu/include/nvgpu/vm_area.h b/drivers/gpu/nvgpu/include/nvgpu/vm_area.h
index a055ada3..53e1cb85 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/vm_area.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/vm_area.h
@@ -60,8 +60,8 @@ nvgpu_vm_area_from_vm_area_list(struct nvgpu_list_node *node)
 /*
  * Alloc space flags.
  */
-#define NVGPU_VM_AREA_ALLOC_FIXED_OFFSET                (1 << 0)
-#define NVGPU_VM_AREA_ALLOC_SPARSE                      (1 << 1)
+#define NVGPU_VM_AREA_ALLOC_FIXED_OFFSET                BIT(0)
+#define NVGPU_VM_AREA_ALLOC_SPARSE                      BIT(1)
 
 int nvgpu_vm_area_alloc(struct vm_gk20a *vm, u32 pages, u32 page_size,
                         u64 *addr, u32 flags);