gpu: nvgpu: Fix mutex MISRA 17.7 violations

MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch contains fix for calls to nvgpu_mutex_init and
improves related error handling.

JIRA NVGPU-677

Change-Id: I609fa138520cc7ccfdd5aa0e7fd28c8ca0b3a21c
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1805598
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 7 insertions, 7 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/falcon.h b/drivers/gpu/nvgpu/include/nvgpu/falcon.h
index 2920e281..55dca035 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/falcon.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/falcon.h
@@ -29,12 +29,12 @@
 /*
  * Falcon Id Defines
  */
-#define FALCON_ID_PMU       (0)
-#define FALCON_ID_FECS      (2)
-#define FALCON_ID_GPCCS     (3)
-#define FALCON_ID_NVDEC     (4)
-#define FALCON_ID_SEC2      (7)
-#define FALCON_ID_MINION    (10)
+#define FALCON_ID_PMU       (0U)
+#define FALCON_ID_FECS      (2U)
+#define FALCON_ID_GPCCS     (3U)
+#define FALCON_ID_NVDEC     (4U)
+#define FALCON_ID_SEC2      (7U)
+#define FALCON_ID_MINION    (10U)
 
 /*
  * Falcon Base address Defines
@@ -317,6 +317,6 @@ int nvgpu_flcn_queue_push(struct nvgpu_falcon *flcn,
 void nvgpu_flcn_queue_free(struct nvgpu_falcon *flcn,
         struct nvgpu_falcon_queue *queue);
 
-void nvgpu_flcn_sw_init(struct gk20a *g, u32 flcn_id);
+int nvgpu_flcn_sw_init(struct gk20a *g, u32 flcn_id);
 
 #endif /* __FALCON_H__ */