gpu: nvgpu: falcon queue support

-Renamed "struct pmu_queue" to "struct
 nvgpu_falcon_queue" & moved to falcon.h
-Renamed pmu_queue_* functions to flcn_queue_* &
 moved to new file falcon_queue.c
-Created ops for queue functions in struct
 nvgpu_falcon_queue to support different queue
 types like DMEM/FB-Q.
-Created ops in nvgpu_falcon_engine_dependency_ops
 to add engine specific queue functionality & assigned
 correct HAL functions in hal*.c file.
-Made changes in dependent functions as needed to replace
 struct pmu_queue & calling queue functions using
 nvgpu_falcon_queue data structure.
-Replaced input param "struct nvgpu_pmu *pmu" with
 "struct gk20a *g" for pmu ops pmu_queue_head/pmu_queue_tail
 & also for functions gk20a_pmu_queue_head()/
 gk20a_pmu_queue_tail().
-Made changes in nvgpu_pmu_queue_init() to use nvgpu_falcon_queue
 for PMU queue.
-Modified Makefile to include falcon_queue.o
-Modified Makefile.sources to include falcon_queue.c

Change-Id: I956328f6631b7154267fd5a29eaa1826190d99d1
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1776070
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

3 files changed, 66 insertions, 38 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/falcon.h b/drivers/gpu/nvgpu/include/nvgpu/falcon.h
index 6cfb6670..2920e281 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/falcon.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/falcon.h
@@ -167,6 +167,44 @@ struct gk20a;
 struct nvgpu_falcon;
 struct nvgpu_falcon_bl_info;
 
+struct nvgpu_falcon_queue {
+
+        /* Queue Type (queue_type) */
+        u8 queue_type;
+
+        /* used by nvgpu, for command LPQ/HPQ */
+        struct nvgpu_mutex mutex;
+
+        /* current write position */
+        u32 position;
+        /* physical dmem offset where this queue begins */
+        u32 offset;
+        /* logical queue identifier */
+        u32 id;
+        /* physical queue index */
+        u32 index;
+        /* in bytes */
+        u32 size;
+        /* open-flag */
+        u32 oflag;
+
+        /* queue type(DMEM-Q/FB-Q) specific ops */
+        int (*rewind)(struct nvgpu_falcon *flcn,
+                struct nvgpu_falcon_queue *queue);
+        int (*pop)(struct nvgpu_falcon *flcn,
+                struct nvgpu_falcon_queue *queue, void *data, u32 size,
+                u32 *bytes_read);
+        int (*push)(struct nvgpu_falcon *flcn,
+                struct nvgpu_falcon_queue *queue, void *data, u32 size);
+        bool (*has_room)(struct nvgpu_falcon *flcn,
+                struct nvgpu_falcon_queue *queue, u32 size,
+                bool *need_rewind);
+        int (*tail)(struct nvgpu_falcon *flcn,
+                struct nvgpu_falcon_queue *queue, u32 *tail, bool set);
+        int (*head)(struct nvgpu_falcon *flcn,
+                struct nvgpu_falcon_queue *queue, u32 *head, bool set);
+};
+
 struct nvgpu_falcon_version_ops {
         void (*start_cpu_secure)(struct nvgpu_falcon *flcn);
         void (*write_dmatrfbase)(struct nvgpu_falcon *flcn, u32 addr);
@@ -175,6 +213,11 @@ struct nvgpu_falcon_version_ops {
 /* ops which are falcon engine specific */
 struct nvgpu_falcon_engine_dependency_ops {
         int (*reset_eng)(struct gk20a *g);
+        int (*queue_head)(struct gk20a *g, struct nvgpu_falcon_queue *queue,
+                u32 *head, bool set);
+        int (*queue_tail)(struct gk20a *g, struct nvgpu_falcon_queue *queue,
+                u32 *tail, bool set);
+        void (*msgq_tail)(struct gk20a *g, u32 *tail, bool set);
 };
 
 struct nvgpu_falcon_ops {
@@ -259,6 +302,21 @@ void nvgpu_flcn_dump_stats(struct nvgpu_falcon *flcn);
 int nvgpu_flcn_bl_bootstrap(struct nvgpu_falcon *flcn,
         struct nvgpu_falcon_bl_info *bl_info);
 
+/* queue public functions */
+int nvgpu_flcn_queue_init(struct nvgpu_falcon *flcn,
+        struct nvgpu_falcon_queue *queue);
+bool nvgpu_flcn_queue_is_empty(struct nvgpu_falcon *flcn,
+        struct nvgpu_falcon_queue *queue);
+int nvgpu_flcn_queue_rewind(struct nvgpu_falcon *flcn,
+        struct nvgpu_falcon_queue *queue);
+int nvgpu_flcn_queue_pop(struct nvgpu_falcon *flcn,
+        struct nvgpu_falcon_queue *queue, void *data, u32 size,
+        u32 *bytes_read);
+int nvgpu_flcn_queue_push(struct nvgpu_falcon *flcn,
+        struct nvgpu_falcon_queue *queue, void *data, u32 size);
+void nvgpu_flcn_queue_free(struct nvgpu_falcon *flcn,
+        struct nvgpu_falcon_queue *queue);
+
 void nvgpu_flcn_sw_init(struct gk20a *g, u32 flcn_id);
 
 #endif /* __FALCON_H__ */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmu.h
index 507b8133..4d1bf75a 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/pmu.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmu.h
@@ -32,6 +32,7 @@
 #include <nvgpu/nvgpu_common.h>
 #include <nvgpu/flcnif_cmn.h>
 #include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
+#include <nvgpu/falcon.h>
 
 #define nvgpu_pmu_dbg(g, fmt, args...) \
         nvgpu_log(g, gpu_dbg_pmu, fmt, ##args)
@@ -266,30 +267,6 @@ struct pmu_ucode_desc_v1 {
         u32 compressed;
 };
 
-struct pmu_queue {
-
-        /* used by hw, for BIOS/SMI queue */
-        u32 mutex_id;
-        u32 mutex_lock;
-        /* used by sw, for LPQ/HPQ queue */
-        struct nvgpu_mutex mutex;
-
-        /* current write position */
-        u32 position;
-        /* physical dmem offset where this queue begins */
-        u32 offset;
-        /* logical queue identifier */
-        u32 id;
-        /* physical queue index */
-        u32 index;
-        /* in bytes */
-        u32 size;
-
-        /* open-flag */
-        u32 oflag;
-        bool opened; /* opened implies locked */
-};
-
 struct pmu_mutex {
         u32 id;
         u32 index;
@@ -345,7 +322,7 @@ struct nvgpu_pmu {
 
         struct pmu_sha1_gid gid_info;
 
-        struct pmu_queue queue[PMU_QUEUE_COUNT];
+        struct nvgpu_falcon_queue queue[PMU_QUEUE_COUNT];
 
         struct pmu_sequence *seq;
         unsigned long pmu_seq_tbl[PMU_SEQ_TBL_SIZE];
@@ -450,7 +427,6 @@ int nvgpu_pmu_mutex_release(struct nvgpu_pmu *pmu, u32 id, u32 *token);
 
 int nvgpu_pmu_queue_init(struct nvgpu_pmu *pmu, u32 id,
         union pmu_init_msg_pmu *init);
-bool nvgpu_pmu_queue_is_empty(struct nvgpu_pmu *pmu, struct pmu_queue *queue);
 
 /* send a cmd to pmu */
 int nvgpu_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd,
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_cmn.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_cmn.h
index 2284289e..68df80b4 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_cmn.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_cmn.h
@@ -27,15 +27,11 @@
  * commands to the PMU
  */
 /* write by sw, read by pmu, protected by sw mutex lock */
-#define PMU_COMMAND_QUEUE_HPQ           0
+#define PMU_COMMAND_QUEUE_HPQ           0U
 /* write by sw, read by pmu, protected by sw mutex lock */
-#define PMU_COMMAND_QUEUE_LPQ           1
-/* read/write by sw/hw, protected by hw pmu mutex, id = 2 */
-#define PMU_COMMAND_QUEUE_BIOS          2
-/* read/write by sw/hw, protected by hw pmu mutex, id = 3 */
-#define PMU_COMMAND_QUEUE_SMI           3
+#define PMU_COMMAND_QUEUE_LPQ           1U
 /* write by pmu, read by sw, accessed by interrupt handler, no lock */
-#define PMU_MESSAGE_QUEUE               4
+#define PMU_MESSAGE_QUEUE               4U
 #define PMU_QUEUE_COUNT                 5
 
 #define PMU_IS_COMMAND_QUEUE(id)        \
@@ -48,15 +44,13 @@
 #define  PMU_IS_MESSAGE_QUEUE(id)       \
                 ((id) == PMU_MESSAGE_QUEUE)
 
-enum {
-        OFLAG_READ = 0,
-        OFLAG_WRITE
-};
+#define OFLAG_READ      0U
+#define OFLAG_WRITE     1U
 
 #define QUEUE_SET               (true)
 #define QUEUE_GET               (false)
 
-#define QUEUE_ALIGNMENT         (4)
+#define QUEUE_ALIGNMENT         (4U)
 
 /* An enumeration containing all valid logical mutex identifiers */
 enum {