gpu: nvgpu: Cleanup generic MM code in gk20a/mm_gk20a.c

Move much of the remaining generic MM code to a new common location:
common/mm/mm.c. Also add a corresponding <nvgpu/mm.h> header. This
mostly consists of init and cleanup code to handle the common MM
data structures like the VIDMEM code, address spaces for various
engines, etc.

A few more indepth changes were made as well.

1. alloc_inst_block() has been added to the MM HAL. This used to be
   defined directly in the gk20a code but it used a register. As a
   result, if this register hypothetically changes in the future,
   it would need to become a HAL anyway. This path preempts that
   and for now just defines all HALs to use the gk20a version.

2. Rename as much as possible: global functions are, for the most
   part, prepended with nvgpu (there are a few exceptions which I
   have yet to decide what to do with). Functions that are static
   are renamed to be as consistent with their functionality as
   possible since in some cases function effect and function name
   have diverged.

JIRA NVGPU-30

Change-Id: Ic948f1ecc2f7976eba4bb7169a44b7226bb7c0b5
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1574499
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 220 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/mm.h b/drivers/gpu/nvgpu/include/nvgpu/mm.h
new file mode 100644
index 00000000..13b33d9f
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/mm.h
@@ -0,0 +1,220 @@
+/*
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_MM_H__
+#define __NVGPU_MM_H__
+
+#include <nvgpu/types.h>
+#include <nvgpu/cond.h>
+#include <nvgpu/thread.h>
+#include <nvgpu/lock.h>
+#include <nvgpu/atomic.h>
+#include <nvgpu/nvgpu_mem.h>
+#include <nvgpu/allocator.h>
+#include <nvgpu/list.h>
+
+struct gk20a;
+struct vm_gk20a;
+struct nvgpu_mem;
+struct nvgpu_pd_cache;
+
+#define FAULT_TYPE_NUM          2       /* replay and nonreplay faults */
+
+struct mmu_fault_info {
+        u64     inst_ptr;
+        u32     inst_aperture;
+        u64     fault_addr;
+        u32     fault_addr_aperture;
+        u32     timestamp_lo;
+        u32     timestamp_hi;
+        u32     mmu_engine_id;
+        u32     gpc_id;
+        u32     client_type;
+        u32     client_id;
+        u32     fault_type;
+        u32     access_type;
+        u32     protected_mode;
+        u32     replayable_fault;
+        u32     replay_fault_en;
+        u32     valid;
+        u32     faulted_pbdma;
+        u32     faulted_engine;
+        u32     faulted_subid;
+        u32     chid;
+        struct channel_gk20a *refch;
+        const char *client_type_desc;
+        const char *fault_type_desc;
+        const char *client_id_desc;
+};
+
+enum nvgpu_flush_op {
+        NVGPU_FLUSH_DEFAULT,
+        NVGPU_FLUSH_FB,
+        NVGPU_FLUSH_L2_INV,
+        NVGPU_FLUSH_L2_FLUSH,
+        NVGPU_FLUSH_CBC_CLEAN,
+};
+
+struct mm_gk20a {
+        struct gk20a *g;
+
+        /* GPU VA default sizes address spaces for channels */
+        struct {
+                u64 user_size;   /* userspace-visible GPU VA region */
+                u64 kernel_size; /* kernel-only GPU VA region */
+        } channel;
+
+        struct {
+                u32 aperture_size;
+                struct vm_gk20a *vm;
+                struct nvgpu_mem inst_block;
+        } bar1;
+
+        struct {
+                u32 aperture_size;
+                struct vm_gk20a *vm;
+                struct nvgpu_mem inst_block;
+        } bar2;
+
+        struct {
+                u32 aperture_size;
+                struct vm_gk20a *vm;
+                struct nvgpu_mem inst_block;
+        } pmu;
+
+        struct {
+                /* using pmu vm currently */
+                struct nvgpu_mem inst_block;
+        } hwpm;
+
+        struct {
+                struct vm_gk20a *vm;
+                struct nvgpu_mem inst_block;
+        } perfbuf;
+
+        struct {
+                struct vm_gk20a *vm;
+        } cde;
+
+        struct {
+                struct vm_gk20a *vm;
+        } ce;
+
+        struct nvgpu_pd_cache *pd_cache;
+
+        struct nvgpu_mutex l2_op_lock;
+        struct nvgpu_mutex tlb_lock;
+        struct nvgpu_mutex priv_lock;
+
+        struct nvgpu_mem bar2_desc;
+
+#ifdef CONFIG_TEGRA_19x_GPU
+        struct nvgpu_mem hw_fault_buf[FAULT_TYPE_NUM];
+        unsigned int hw_fault_buf_status[FAULT_TYPE_NUM];
+        struct mmu_fault_info *fault_info[FAULT_TYPE_NUM];
+        struct nvgpu_mutex hub_isr_mutex;
+        u32    hub_intr_types;
+#endif
+        /*
+         * Separate function to cleanup the CE since it requires a channel to
+         * be closed which must happen before fifo cleanup.
+         */
+        void (*remove_ce_support)(struct mm_gk20a *mm);
+        void (*remove_support)(struct mm_gk20a *mm);
+        bool sw_ready;
+        int physical_bits;
+        bool use_full_comp_tag_line;
+        bool ltc_enabled_current;
+        bool ltc_enabled_target;
+        bool bypass_smmu;
+        bool disable_bigpage;
+        bool has_physical_mode;
+
+        struct nvgpu_mem sysmem_flush;
+
+        u32 pramin_window;
+        struct nvgpu_spinlock pramin_window_lock;
+        bool force_pramin; /* via debugfs */
+
+        struct {
+                size_t size;
+                u64 base;
+                size_t bootstrap_size;
+                u64 bootstrap_base;
+
+                struct nvgpu_allocator allocator;
+                struct nvgpu_allocator bootstrap_allocator;
+
+                u32 ce_ctx_id;
+                volatile bool cleared;
+                struct nvgpu_mutex first_clear_mutex;
+
+                struct nvgpu_list_node clear_list_head;
+                struct nvgpu_mutex clear_list_mutex;
+
+                struct nvgpu_cond clearing_thread_cond;
+                struct nvgpu_thread clearing_thread;
+                struct nvgpu_mutex clearing_thread_lock;
+                nvgpu_atomic_t pause_count;
+
+                nvgpu_atomic64_t bytes_pending;
+        } vidmem;
+};
+
+#define gk20a_from_mm(mm) ((mm)->g)
+#define gk20a_from_vm(vm) ((vm)->mm->g)
+
+static inline int bar1_aperture_size_mb_gk20a(void)
+{
+        return 16; /* 16MB is more than enough atm. */
+}
+
+/* The maximum GPU VA range supported */
+#define NV_GMMU_VA_RANGE          38
+
+/* The default userspace-visible GPU VA size */
+#define NV_MM_DEFAULT_USER_SIZE   (1ULL << 37)
+
+/* The default kernel-reserved GPU VA size */
+#define NV_MM_DEFAULT_KERNEL_SIZE (1ULL << 32)
+
+/*
+ * When not using unified address spaces, the bottom 56GB of the space are used
+ * for small pages, and the remaining high memory is used for large pages.
+ */
+static inline u64 __nv_gmmu_va_small_page_limit(void)
+{
+        return ((u64)SZ_1G * 56);
+}
+
+enum gmmu_pgsz_gk20a __get_pte_size_fixed_map(struct vm_gk20a *vm,
+                                              u64 base, u64 size);
+enum gmmu_pgsz_gk20a __get_pte_size(struct vm_gk20a *vm, u64 base, u64 size);
+
+void nvgpu_init_mm_ce_context(struct gk20a *g);
+int nvgpu_init_mm_support(struct gk20a *g);
+int nvgpu_init_mm_setup_hw(struct gk20a *g);
+
+u64 nvgpu_inst_block_addr(struct gk20a *g, struct nvgpu_mem *mem);
+void nvgpu_free_inst_block(struct gk20a *g, struct nvgpu_mem *inst_block);
+
+int nvgpu_mm_suspend(struct gk20a *g);
+
+#endif