gpu: nvgpu: gv11b: Correct PMU PG enabled masks.

PMU ucode records supported feature list for a
particular chip as support mask sent
via PMU_PG_PARAM_CMD_GR_INIT_PARAM.

It then enables selective feature list through
enable mask sent via
PMU_PG_PARAM_CMD_SUB_FEATURE_MASK_UPDATE cmd.

Right now only ELPG state machine mask was enabled.
Only ELPG state machine was getting executed
but other crucial steps in ELPG entry/exit sequence
were getting skipped.

Bug 200392620.
Bug 200296076.

Change-Id: I5e1800980990c146c731537290cb7d4c07e937c3
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1665767
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 22 insertions, 5 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h
index b1077821..91656156 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h
@@ -128,14 +128,31 @@ enum {
 #define PMU_PG_PARAM_CMD_POST_INIT  0x06
 #define PMU_PG_PARAM_CMD_SUB_FEATURE_MASK_UPDATE  0x07
 
-#define PMU_PG_FEATURE_GR_SDIV_SLOWDOWN_ENABLED (1 << 0)
-#define PMU_PG_FEATURE_GR_POWER_GATING_ENABLED  (1 << 2)
-#define PMU_PG_FEATURE_GR_RPPG_ENABLED          (1 << 3)
+#define NVGPU_PMU_GR_FEATURE_MASK_SDIV_SLOWDOWN     (1 << 0)
+#define NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING      (1 << 2)
+#define NVGPU_PMU_GR_FEATURE_MASK_RPPG              (1 << 3)
+#define NVGPU_PMU_GR_FEATURE_MASK_PRIV_RING         (1 << 5)
+#define NVGPU_PMU_GR_FEATURE_MASK_UNBIND            (1 << 6)
+#define NVGPU_PMU_GR_FEATURE_MASK_SAVE_GLOBAL_STATE (1 << 7)
+#define NVGPU_PMU_GR_FEATURE_MASK_RESET_ENTRY       (1 << 8)
+#define NVGPU_PMU_GR_FEATURE_MASK_HW_SEQUENCE       (1 << 9)
+#define NVGPU_PMU_GR_FEATURE_MASK_ELPG_SRAM         (1 << 10)
+#define NVGPU_PMU_GR_FEATURE_MASK_ELPG_LOGIC        (1 << 11)
+#define NVGPU_PMU_GR_FEATURE_MASK_ELPG_L2RPPG       (1 << 12)
 
-#define NVGPU_PMU_GR_FEATURE_MASK_RPPG  (1 << 3)
 #define NVGPU_PMU_GR_FEATURE_MASK_ALL   \
         (       \
-                NVGPU_PMU_GR_FEATURE_MASK_RPPG   \
+                NVGPU_PMU_GR_FEATURE_MASK_SDIV_SLOWDOWN         |\
+                NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING          |\
+                NVGPU_PMU_GR_FEATURE_MASK_RPPG                  |\
+                NVGPU_PMU_GR_FEATURE_MASK_PRIV_RING             |\
+                NVGPU_PMU_GR_FEATURE_MASK_UNBIND                |\
+                NVGPU_PMU_GR_FEATURE_MASK_SAVE_GLOBAL_STATE     |\
+                NVGPU_PMU_GR_FEATURE_MASK_RESET_ENTRY           |\
+                NVGPU_PMU_GR_FEATURE_MASK_HW_SEQUENCE           |\
+                NVGPU_PMU_GR_FEATURE_MASK_ELPG_SRAM             |\
+                NVGPU_PMU_GR_FEATURE_MASK_ELPG_LOGIC            |\
+                NVGPU_PMU_GR_FEATURE_MASK_ELPG_L2RPPG           \
         )
 
 #define NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING  (1 << 0)