diff options
author | Deepak Goyal <dgoyal@nvidia.com> | 2018-02-28 06:09:57 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-03-06 00:18:20 -0500 |
commit | 26b91946031a88293c7ce563ff923802af6509ce (patch) | |
tree | 9b7ad56e7feb381b903f0c07a988114cdec0302f /drivers/gpu/nvgpu/include | |
parent | 848af2ce6de6140323a6ffe3075bf8021e119434 (diff) |
gpu: nvgpu: gv11b: Correct PMU PG enabled masks.
PMU ucode records supported feature list for a
particular chip as support mask sent
via PMU_PG_PARAM_CMD_GR_INIT_PARAM.
It then enables selective feature list through
enable mask sent via
PMU_PG_PARAM_CMD_SUB_FEATURE_MASK_UPDATE cmd.
Right now only ELPG state machine mask was enabled.
Only ELPG state machine was getting executed
but other crucial steps in ELPG entry/exit sequence
were getting skipped.
Bug 200392620.
Bug 200296076.
Change-Id: I5e1800980990c146c731537290cb7d4c07e937c3
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1665767
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h | 27 |
1 files changed, 22 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h index b1077821..91656156 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h | |||
@@ -128,14 +128,31 @@ enum { | |||
128 | #define PMU_PG_PARAM_CMD_POST_INIT 0x06 | 128 | #define PMU_PG_PARAM_CMD_POST_INIT 0x06 |
129 | #define PMU_PG_PARAM_CMD_SUB_FEATURE_MASK_UPDATE 0x07 | 129 | #define PMU_PG_PARAM_CMD_SUB_FEATURE_MASK_UPDATE 0x07 |
130 | 130 | ||
131 | #define PMU_PG_FEATURE_GR_SDIV_SLOWDOWN_ENABLED (1 << 0) | 131 | #define NVGPU_PMU_GR_FEATURE_MASK_SDIV_SLOWDOWN (1 << 0) |
132 | #define PMU_PG_FEATURE_GR_POWER_GATING_ENABLED (1 << 2) | 132 | #define NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING (1 << 2) |
133 | #define PMU_PG_FEATURE_GR_RPPG_ENABLED (1 << 3) | 133 | #define NVGPU_PMU_GR_FEATURE_MASK_RPPG (1 << 3) |
134 | #define NVGPU_PMU_GR_FEATURE_MASK_PRIV_RING (1 << 5) | ||
135 | #define NVGPU_PMU_GR_FEATURE_MASK_UNBIND (1 << 6) | ||
136 | #define NVGPU_PMU_GR_FEATURE_MASK_SAVE_GLOBAL_STATE (1 << 7) | ||
137 | #define NVGPU_PMU_GR_FEATURE_MASK_RESET_ENTRY (1 << 8) | ||
138 | #define NVGPU_PMU_GR_FEATURE_MASK_HW_SEQUENCE (1 << 9) | ||
139 | #define NVGPU_PMU_GR_FEATURE_MASK_ELPG_SRAM (1 << 10) | ||
140 | #define NVGPU_PMU_GR_FEATURE_MASK_ELPG_LOGIC (1 << 11) | ||
141 | #define NVGPU_PMU_GR_FEATURE_MASK_ELPG_L2RPPG (1 << 12) | ||
134 | 142 | ||
135 | #define NVGPU_PMU_GR_FEATURE_MASK_RPPG (1 << 3) | ||
136 | #define NVGPU_PMU_GR_FEATURE_MASK_ALL \ | 143 | #define NVGPU_PMU_GR_FEATURE_MASK_ALL \ |
137 | ( \ | 144 | ( \ |
138 | NVGPU_PMU_GR_FEATURE_MASK_RPPG \ | 145 | NVGPU_PMU_GR_FEATURE_MASK_SDIV_SLOWDOWN |\ |
146 | NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING |\ | ||
147 | NVGPU_PMU_GR_FEATURE_MASK_RPPG |\ | ||
148 | NVGPU_PMU_GR_FEATURE_MASK_PRIV_RING |\ | ||
149 | NVGPU_PMU_GR_FEATURE_MASK_UNBIND |\ | ||
150 | NVGPU_PMU_GR_FEATURE_MASK_SAVE_GLOBAL_STATE |\ | ||
151 | NVGPU_PMU_GR_FEATURE_MASK_RESET_ENTRY |\ | ||
152 | NVGPU_PMU_GR_FEATURE_MASK_HW_SEQUENCE |\ | ||
153 | NVGPU_PMU_GR_FEATURE_MASK_ELPG_SRAM |\ | ||
154 | NVGPU_PMU_GR_FEATURE_MASK_ELPG_LOGIC |\ | ||
155 | NVGPU_PMU_GR_FEATURE_MASK_ELPG_L2RPPG \ | ||
139 | ) | 156 | ) |
140 | 157 | ||
141 | #define NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING (1 << 0) | 158 | #define NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING (1 << 0) |