gpu: nvgpu: Multiple WPR support

The WPR will be divided into several sub-WPRs,
one for each Falcon and one common for sharing
between Falcons which bootstrap falcons

- Defined & used flag NVGPU_SUPPORT_MULTIPLE_WPR
  to know M-WPR support.
- Added struct lsfm_sub_wpr to hold subWPR header info
- Added struct lsf_shared_sub_wpr_header to hold subWPR
  info & copied to WPR blob after LSF_WPR_HEADER
- Set NVGPU_SUPPORT_MULTIPLE_WPR to false for gp106,
  gv100 & gv11b.
- Added methods to support to multiple WPR support &
  called by checking flag NVGPU_SUPPORT_MULTIPLE_WPR
  in ucode blob preparation flow.

JIRA NVGPUTU10X / NVGPUT-99

Change-Id: I81d0490158390e79b6841374158805f7a84ee6cb
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1725369
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

3 files changed, 101 insertions, 7 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h b/drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h
index 70184934..90d2d20d 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -28,6 +28,22 @@
 #endif
 
 /*
+ * READ/WRITE masks for WPR region
+ */
+/* Readable only from level 2 and 3 client */
+#define LSF_WPR_REGION_RMASK    (0xC)
+/* Writable only from level 2 and 3 client */
+#define LSF_WPR_REGION_WMASK    (0xC)
+/* Readable only from level 3 client */
+#define LSF_WPR_REGION_RMASK_SUB_WPR_ENABLED    (0x8)
+/* Writable only from level 3 client */
+#define LSF_WPR_REGION_WMASK_SUB_WPR_ENABLED    (0x8)
+/* Disallow read mis-match for all clients */
+#define LSF_WPR_REGION_ALLOW_READ_MISMATCH_NO   (0x0)
+/* Disallow write mis-match for all clients */
+#define LSF_WPR_REGION_ALLOW_WRITE_MISMATCH_NO  (0x0)
+
+/*
  * Falcon Id Defines
  * Defines a common Light Secure Falcon identifier.
  */
@@ -84,6 +100,42 @@ struct lsf_wpr_header_v1 {
         u32 bin_version;
         u32 status;
 };
+
+
+/*
+ * LSF shared SubWpr Header
+ *
+ * use_case_id - Shared SubWpr use case ID (updated by nvgpu)
+ * start_addr  - start address of subWpr (updated by nvgpu)
+ * size_4K     - size of subWpr in 4K (updated by nvgpu)
+ */
+struct lsf_shared_sub_wpr_header {
+        u32 use_case_id;
+        u32 start_addr;
+        u32 size_4K;
+};
+
+/* shared sub_wpr use case IDs */
+enum {
+        LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_FRTS_VBIOS_TABLES   = 1,
+        LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_PLAYREADY_SHARED_DATA = 2
+};
+
+#define LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX \
+        LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_PLAYREADY_SHARED_DATA
+
+#define LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_INVALID     (0xFFFFFFFF)
+
+#define MAX_SUPPORTED_SHARED_SUB_WPR_USE_CASES  \
+        LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX
+
+/* Static sizes of shared subWPRs */
+/* Minimum granularity supported is 4K */
+/* 1MB in 4K */
+#define LSF_SHARED_DATA_SUB_WPR_FRTS_VBIOS_TABLES_SIZE_IN_4K    (0x100)
+/* 4K */
+#define LSF_SHARED_DATA_SUB_WPR_PLAYREADY_SHARED_DATA_SIZE_IN_4K        (0x1)
+
 /*
  * Bootstrap Owner Defines
  */
@@ -147,13 +199,40 @@ struct lsf_lsb_header_v1 {
 /*
  * Light Secure WPR Content Alignments
  */
-#define LSF_LSB_HEADER_ALIGNMENT    256
-#define LSF_BL_DATA_ALIGNMENT       256
-#define LSF_BL_DATA_SIZE_ALIGNMENT  256
-#define LSF_BL_CODE_SIZE_ALIGNMENT  256
+#define LSF_WPR_HEADER_ALIGNMENT        (256U)
+#define LSF_SUB_WPR_HEADER_ALIGNMENT    (256U)
+#define LSF_LSB_HEADER_ALIGNMENT        (256U)
+#define LSF_BL_DATA_ALIGNMENT           (256U)
+#define LSF_BL_DATA_SIZE_ALIGNMENT      (256U)
+#define LSF_BL_CODE_SIZE_ALIGNMENT      (256U)
+#define LSF_DATA_SIZE_ALIGNMENT         (256U)
+#define LSF_CODE_SIZE_ALIGNMENT         (256U)
+
+/* MMU excepts sub_wpr sizes in units of 4K */
+#define SUB_WPR_SIZE_ALIGNMENT  (4096U)
+
+/*
+ * Maximum WPR Header size
+ */
+#define LSF_WPR_HEADERS_TOTAL_SIZE_MAX  \
+        (ALIGN_UP((sizeof(struct lsf_wpr_header_v1) * LSF_FALCON_ID_END), \
+                LSF_WPR_HEADER_ALIGNMENT))
+#define LSF_LSB_HEADER_TOTAL_SIZE_MAX   (\
+        ALIGN_UP(sizeof(struct lsf_lsb_header_v1), LSF_LSB_HEADER_ALIGNMENT))
+
+/* Maximum SUB WPR header size */
+#define LSF_SUB_WPR_HEADERS_TOTAL_SIZE_MAX      (ALIGN_UP( \
+        (sizeof(struct lsf_shared_sub_wpr_header) * \
+        LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX), \
+        LSF_SUB_WPR_HEADER_ALIGNMENT))
+
 
 #define LSF_UCODE_DATA_ALIGNMENT 4096
 
+/* Defined for 1MB alignment */
+#define SHIFT_1MB       (20)
+#define SHIFT_4KB       (12)
+
 /*
  * Supporting maximum of 2 regions.
  * This is needed to pre-allocate space in DMEM
diff --git a/drivers/gpu/nvgpu/include/nvgpu/acr/acr_objlsfm.h b/drivers/gpu/nvgpu/include/nvgpu/acr/acr_objlsfm.h
index cde8707a..96fb9f19 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/acr/acr_objlsfm.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/acr/acr_objlsfm.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -73,12 +73,24 @@ struct ls_flcn_mgr {
         void *wpr_client_req_state;/*PACR_CLIENT_REQUEST_STATE originally*/
 };
 
+/*
+ * LSFM SUB WPRs struct
+ * pnext        : Next entry in the list, NULL if last
+ * sub_wpr_header : SubWpr Header struct
+ */
+struct lsfm_sub_wpr {
+        struct lsfm_sub_wpr *pnext;
+        struct lsf_shared_sub_wpr_header sub_wpr_header;
+};
+
 struct ls_flcn_mgr_v1 {
         u16 managed_flcn_cnt;
         u32 wpr_size;
         u32 disable_mask;
         struct lsfm_managed_ucode_img_v2 *ucode_img_list;
         void *wpr_client_req_state;/*PACR_CLIENT_REQUEST_STATE originally*/
+        u16 managed_sub_wpr_count;
+        struct lsfm_sub_wpr *psub_wpr_list;
 };
 
 
diff --git a/drivers/gpu/nvgpu/include/nvgpu/enabled.h b/drivers/gpu/nvgpu/include/nvgpu/enabled.h
index a76db09e..0ffb0488 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/enabled.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/enabled.h
@@ -163,10 +163,13 @@ struct gk20a;
 /* USERMODE enable bit */
 #define NVGPU_SUPPORT_USERMODE_SUBMIT           67
 
+/* Multiple WPR support */
+#define NVGPU_SUPPORT_MULTIPLE_WPR      68
+
 /*
  * Must be greater than the largest bit offset in the above list.
  */
-#define NVGPU_MAX_ENABLED_BITS                  68
+#define NVGPU_MAX_ENABLED_BITS                  69
 
 /**
  * nvgpu_is_enabled - Check if the passed flag is enabled.