gpu: nvgpu: move channel_sync_gk20a.* to common directory

1) Move channel_sync_gk20a.* from gk20a/ to common/ directory as they
donot program any hardware registers. Also as an add-on rename
channel_sync_gk20a.* to channel_sync.* and update the headers
in required files.
2) Rename the struct gk20a_channel_sync to struct nvgpu_channel_sync. Also,
corresponding syncpt and semaphore versions of the struct alongwith
related methods are renamed by removing "gk20a" from their names and
adding "nvgpu".
3) Add misra-c cleanups

Jira NVGPU-1086

Change-Id: I4e0e21803ca3858dd7a5fc4d2454dba1f1bfcecd
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1812594
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2 files changed, 116 insertions, 3 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/channel.h b/drivers/gpu/nvgpu/include/nvgpu/channel.h
index 6cca843e..cd4fadf8 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/channel.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/channel.h
@@ -35,7 +35,7 @@ struct gk20a;
 struct dbg_session_gk20a;
 struct gk20a_fence;
 struct fifo_profile_gk20a;
-struct gk20a_channel_sync;
+struct nvgpu_channel_sync;
 struct nvgpu_gpfifo_userdata;
 
 /* Flags to be passed to gk20a_channel_alloc_gpfifo() */
@@ -289,8 +289,8 @@ struct channel_gk20a {
         struct nvgpu_list_node dbg_s_list;
 
         struct nvgpu_mutex sync_lock;
-        struct gk20a_channel_sync *sync;
-        struct gk20a_channel_sync *user_sync;
+        struct nvgpu_channel_sync *sync;
+        struct nvgpu_channel_sync *user_sync;
 
 #ifdef CONFIG_TEGRA_GR_VIRTUALIZATION
         u64 virt_ctx;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/channel_sync.h b/drivers/gpu/nvgpu/include/nvgpu/channel_sync.h
new file mode 100644
index 00000000..b5936edc
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/channel_sync.h
@@ -0,0 +1,113 @@
+/*
+ *
+ * Nvgpu Channel Synchronization Abstraction
+ *
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_CHANNEL_SYNC_H
+#define NVGPU_CHANNEL_SYNC_H
+
+#include <nvgpu/atomic.h>
+
+struct nvgpu_channel_sync;
+struct priv_cmd_entry;
+struct channel_gk20a;
+struct gk20a_fence;
+struct gk20a;
+struct nvgpu_semaphore;
+
+struct nvgpu_channel_sync {
+        nvgpu_atomic_t refcount;
+
+        /* Generate a gpu wait cmdbuf from syncpoint.
+         * Returns a gpu cmdbuf that performs the wait when executed
+         */
+        int (*wait_syncpt)(struct nvgpu_channel_sync *s, u32 id, u32 thresh,
+                           struct priv_cmd_entry *entry);
+
+        /* Generate a gpu wait cmdbuf from sync fd.
+         * Returns a gpu cmdbuf that performs the wait when executed
+         */
+        int (*wait_fd)(struct nvgpu_channel_sync *s, int fd,
+                       struct priv_cmd_entry *entry, int max_wait_cmds);
+
+        /* Increment syncpoint/semaphore.
+         * Returns
+         *  - a gpu cmdbuf that performs the increment when executed,
+         *  - a fence that can be passed to wait_cpu() and is_expired().
+         */
+        int (*incr)(struct nvgpu_channel_sync *s,
+                    struct priv_cmd_entry *entry,
+                    struct gk20a_fence *fence,
+                    bool need_sync_fence,
+                    bool register_irq);
+
+        /* Increment syncpoint/semaphore, so that the returned fence represents
+         * work completion (may need wfi) and can be returned to user space.
+         * Returns
+         *  - a gpu cmdbuf that performs the increment when executed,
+         *  - a fence that can be passed to wait_cpu() and is_expired(),
+         *  - a gk20a_fence that signals when the incr has happened.
+         */
+        int (*incr_user)(struct nvgpu_channel_sync *s,
+                         int wait_fence_fd,
+                         struct priv_cmd_entry *entry,
+                         struct gk20a_fence *fence,
+                         bool wfi,
+                         bool need_sync_fence,
+                         bool register_irq);
+
+        /* Reset the channel syncpoint/semaphore. */
+        void (*set_min_eq_max)(struct nvgpu_channel_sync *s);
+
+        /*
+         * Set the channel syncpoint/semaphore to safe state
+         * This should be used to reset User managed syncpoint since we don't
+         * track threshold values for those syncpoints
+         */
+        void (*set_safe_state)(struct nvgpu_channel_sync *s);
+
+        /* Returns the sync point id or negative number if no syncpt*/
+        int (*syncpt_id)(struct nvgpu_channel_sync *s);
+
+        /* Returns the sync point address of sync point or 0 if not supported */
+        u64 (*syncpt_address)(struct nvgpu_channel_sync *s);
+
+        /* Free the resources allocated by nvgpu_channel_sync_create. */
+        void (*destroy)(struct nvgpu_channel_sync *s);
+};
+
+void channel_sync_semaphore_gen_wait_cmd(struct channel_gk20a *c,
+        struct nvgpu_semaphore *sema, struct priv_cmd_entry *wait_cmd,
+        u32 wait_cmd_size, int pos);
+
+int channel_sync_syncpt_gen_wait_cmd(struct channel_gk20a *c,
+                u32 id, u32 thresh, struct priv_cmd_entry *wait_cmd,
+                u32 wait_cmd_size, int pos, bool preallocated);
+
+void nvgpu_channel_sync_destroy(struct nvgpu_channel_sync *sync,
+        bool set_safe_state);
+struct nvgpu_channel_sync *nvgpu_channel_sync_create(struct channel_gk20a *c,
+        bool user_managed);
+bool nvgpu_channel_sync_needs_os_fence_framework(struct gk20a *g);
+
+#endif /* NVGPU_GK20A_CHANNEL_SYNC_GK20A_H */