gpu: nvgpu: Update clk_fll interface as per chips_a

Two new members added to fll struct and code modified to support
GV100 VBIOS NAFLL tables
Add g->ops for getting vbios clk domains

JIRA NVGPUGV100-39

Change-Id: Iaabea893d55d44a272e2bce2b1d525b122cd36f5
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1594289
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Tested-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2 files changed, 5 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/bios.h b/drivers/gpu/nvgpu/include/nvgpu/bios.h
index 86e009a3..191f0dbd 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/bios.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/bios.h
@@ -110,6 +110,9 @@ struct fll_descriptor_entry_10 {
 #define NV_FLL_DESC_FLL_PARAMS_MDIV_MASK 0x1F
 #define NV_FLL_DESC_FLL_PARAMS_MDIV_SHIFT 0
 
+#define NV_FLL_DESC_FLL_PARAMS_SKIP_PLDIV_BELOW_DVCO_MIN_MASK 0x20
+#define NV_FLL_DESC_FLL_PARAMS_SKIP_PLDIV_BELOW_DVCO_MIN_SHIFT 5
+
 #define NV_FLL_DESC_LUT_PARAMS_VSELECT_MASK 0x3
 #define NV_FLL_DESC_LUT_PARAMS_VSELECT_SHIFT 0
 
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h
index 81a1d72e..616aca5c 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h
@@ -230,6 +230,8 @@ struct nv_pmu_clk_clk_fll_device_boardobj_set {
         struct nv_pmu_clk_regime_desc regime_desc;
         u8 min_freq_vfe_idx;
         u8 freq_ctrl_idx;
+        bool b_skip_pldiv_below_dvco_min;
+        bool b_dvco_1x;
         struct ctrl_boardobjgrp_mask_e32 lut_prog_broadcast_slave_mask;
 };