summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/include
diff options
context:
space:
mode:
authorAmulya <Amurthyreddy@nvidia.com>2018-08-09 01:10:08 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-08-22 20:31:33 -0400
commit1c13da1d29c344cb60953eabeca56b601446c64a (patch)
tree145a1a133b2d85592e0ddd1a25b12fc48e879829 /drivers/gpu/nvgpu/include
parentf3c3e4dece89c5e2f77fbfaf3cacd877ba62406c (diff)
gpu: nvgpu: Changed enum gmmu_pgsz_gk20a into macros
Changed the enum gmmu_pgsz_gk20a into macros and changed all the instances of it. The enum gmmu_pgsz_gk20a was being used in for loops, where it was compared with an integer. This violates MISRA rule 10.4, which only allows arithmetic operations on operands of the same essential type category. Changing this enum into macro will fix this violation. JIRA NVGPU-993 Change-Id: I6f18b08bc7548093d99e8229378415bcdec749e3 Signed-off-by: Amulya <Amurthyreddy@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1795593 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/gmmu.h15
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/mm.h4
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/vm.h8
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/vm_area.h2
4 files changed, 13 insertions, 16 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gmmu.h b/drivers/gpu/nvgpu/include/nvgpu/gmmu.h
index 886a79da..a83b0dd8 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gmmu.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gmmu.h
@@ -38,12 +38,10 @@
38struct vm_gk20a; 38struct vm_gk20a;
39struct nvgpu_mem; 39struct nvgpu_mem;
40 40
41enum gmmu_pgsz_gk20a { 41#define GMMU_PAGE_SIZE_SMALL 0U
42 gmmu_page_size_small = 0, 42#define GMMU_PAGE_SIZE_BIG 1U
43 gmmu_page_size_big = 1, 43#define GMMU_PAGE_SIZE_KERNEL 2U
44 gmmu_page_size_kernel = 2, 44#define GMMU_NR_PAGE_SIZES 3U
45 gmmu_nr_page_sizes = 3,
46};
47 45
48enum gk20a_mem_rw_flag { 46enum gk20a_mem_rw_flag {
49 gk20a_mem_flag_none = 0, /* RW */ 47 gk20a_mem_flag_none = 0, /* RW */
@@ -197,9 +195,8 @@ struct gk20a_mmu_level {
197 /* 195 /*
198 * Get pde page size 196 * Get pde page size
199 */ 197 */
200 enum gmmu_pgsz_gk20a (*get_pgsz)(struct gk20a *g, 198 u32 (*get_pgsz)(struct gk20a *g, const struct gk20a_mmu_level *l,
201 const struct gk20a_mmu_level *l, 199 struct nvgpu_gmmu_pd *pd, u32 pd_idx);
202 struct nvgpu_gmmu_pd *pd, u32 pd_idx);
203}; 200};
204 201
205static inline const char *nvgpu_gmmu_perm_str(enum gk20a_mem_rw_flag p) 202static inline const char *nvgpu_gmmu_perm_str(enum gk20a_mem_rw_flag p)
diff --git a/drivers/gpu/nvgpu/include/nvgpu/mm.h b/drivers/gpu/nvgpu/include/nvgpu/mm.h
index 3a1b2a6c..e627296d 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/mm.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/mm.h
@@ -204,9 +204,9 @@ static inline u64 __nv_gmmu_va_small_page_limit(void)
204 return ((u64)SZ_1G * 56); 204 return ((u64)SZ_1G * 56);
205} 205}
206 206
207enum gmmu_pgsz_gk20a __get_pte_size_fixed_map(struct vm_gk20a *vm, 207u32 __get_pte_size_fixed_map(struct vm_gk20a *vm,
208 u64 base, u64 size); 208 u64 base, u64 size);
209enum gmmu_pgsz_gk20a __get_pte_size(struct vm_gk20a *vm, u64 base, u64 size); 209u32 __get_pte_size(struct vm_gk20a *vm, u64 base, u64 size);
210 210
211void nvgpu_init_mm_ce_context(struct gk20a *g); 211void nvgpu_init_mm_ce_context(struct gk20a *g);
212int nvgpu_init_mm_support(struct gk20a *g); 212int nvgpu_init_mm_support(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/include/nvgpu/vm.h b/drivers/gpu/nvgpu/include/nvgpu/vm.h
index 30a2d71d..ad8c7cca 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/vm.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/vm.h
@@ -172,7 +172,7 @@ struct vm_gk20a {
172 * not. vma[] allows the code to be agnostic to this by always using 172 * not. vma[] allows the code to be agnostic to this by always using
173 * address spaces through this pointer array. 173 * address spaces through this pointer array.
174 */ 174 */
175 struct nvgpu_allocator *vma[gmmu_nr_page_sizes]; 175 struct nvgpu_allocator *vma[GMMU_NR_PAGE_SIZES];
176 struct nvgpu_allocator kernel; 176 struct nvgpu_allocator kernel;
177 struct nvgpu_allocator user; 177 struct nvgpu_allocator user;
178 struct nvgpu_allocator user_lp; 178 struct nvgpu_allocator user_lp;
@@ -184,7 +184,7 @@ struct vm_gk20a {
184#ifdef CONFIG_TEGRA_GR_VIRTUALIZATION 184#ifdef CONFIG_TEGRA_GR_VIRTUALIZATION
185 u64 handle; 185 u64 handle;
186#endif 186#endif
187 u32 gmmu_page_sizes[gmmu_nr_page_sizes]; 187 u32 gmmu_page_sizes[GMMU_NR_PAGE_SIZES];
188 188
189 /* if non-NULL, kref_put will use this batch when 189 /* if non-NULL, kref_put will use this batch when
190 unmapping. Must hold vm->update_gmmu_lock. */ 190 unmapping. Must hold vm->update_gmmu_lock. */
@@ -322,8 +322,8 @@ struct vm_gk20a *nvgpu_vm_init(struct gk20a *g,
322 * will be used by the vgpu code. 322 * will be used by the vgpu code.
323 */ 323 */
324u64 __nvgpu_vm_alloc_va(struct vm_gk20a *vm, u64 size, 324u64 __nvgpu_vm_alloc_va(struct vm_gk20a *vm, u64 size,
325 enum gmmu_pgsz_gk20a pgsz_idx); 325 u32 pgsz_idx);
326int __nvgpu_vm_free_va(struct vm_gk20a *vm, u64 addr, 326int __nvgpu_vm_free_va(struct vm_gk20a *vm, u64 addr,
327 enum gmmu_pgsz_gk20a pgsz_idx); 327 u32 pgsz_idx);
328 328
329#endif 329#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/vm_area.h b/drivers/gpu/nvgpu/include/nvgpu/vm_area.h
index 92852633..a055ada3 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/vm_area.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/vm_area.h
@@ -69,7 +69,7 @@ int nvgpu_vm_area_free(struct vm_gk20a *vm, u64 addr);
69 69
70struct nvgpu_vm_area *nvgpu_vm_area_find(struct vm_gk20a *vm, u64 addr); 70struct nvgpu_vm_area *nvgpu_vm_area_find(struct vm_gk20a *vm, u64 addr);
71int nvgpu_vm_area_validate_buffer(struct vm_gk20a *vm, 71int nvgpu_vm_area_validate_buffer(struct vm_gk20a *vm,
72 u64 map_offset, u64 map_size, int pgsz_idx, 72 u64 map_offset, u64 map_size, u32 pgsz_idx,
73 struct nvgpu_vm_area **pvm_area); 73 struct nvgpu_vm_area **pvm_area);
74 74
75#endif 75#endif