gpu: nvgpu: add support to get unicast addresses on volta

We have new broadcast registers on Volta, and we need to generate correct
unicast addresses for them so that we can write those registers to context image

Add new GR HAL create_priv_addr_table() to do this conversion
Set gr_gk20a_create_priv_addr_table() for older chips
Set gr_gv11b_create_priv_addr_table() for Volta

gr_gv11b_create_priv_addr_table() will use the broadcast flags and then generate
appriate list of unicast register for each broadcast register

Bug 200398811
Jira NVGPU-556

Change-Id: Id53a9e56106d200fe560ffc93394cc0e976f455f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1690027
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2 files changed, 50 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h
index 4fbe37cb..268efc52 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -56,6 +56,30 @@
 #ifndef _hw_perf_gv100_h_
 #define _hw_perf_gv100_h_
 
+static inline u32 perf_pmmgpc_perdomain_offset_v(void)
+{
+        return 0x00000200U;
+}
+static inline u32 perf_pmmgpc_base_v(void)
+{
+        return 0x00180000U;
+}
+static inline u32 perf_pmmgpc_extent_v(void)
+{
+        return 0x00183fffU;
+}
+static inline u32 perf_pmmsys_base_v(void)
+{
+        return 0x00240000U;
+}
+static inline u32 perf_pmmsys_extent_v(void)
+{
+        return 0x00243fffU;
+}
+static inline u32 perf_pmmfbp_base_v(void)
+{
+        return 0x00200000U;
+}
 static inline u32 perf_pmasys_control_r(void)
 {
         return 0x0024a000U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h
index 788a6ab6..1d4b2c16 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -56,6 +56,30 @@
 #ifndef _hw_perf_gv11b_h_
 #define _hw_perf_gv11b_h_
 
+static inline u32 perf_pmmgpc_perdomain_offset_v(void)
+{
+        return 0x00000200U;
+}
+static inline u32 perf_pmmgpc_base_v(void)
+{
+        return 0x00180000U;
+}
+static inline u32 perf_pmmgpc_extent_v(void)
+{
+        return 0x00183fffU;
+}
+static inline u32 perf_pmmsys_base_v(void)
+{
+        return 0x00240000U;
+}
+static inline u32 perf_pmmsys_extent_v(void)
+{
+        return 0x00243fffU;
+}
+static inline u32 perf_pmmfbp_base_v(void)
+{
+        return 0x00200000U;
+}
 static inline u32 perf_pmasys_control_r(void)
 {
         return 0x0024a000U;