diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2017-09-13 08:41:52 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-09-15 15:48:20 -0400 |
commit | 460951ed092aad787bacd0ebb0646b799d3463a1 (patch) | |
tree | b7fae8084b76106d77a8af6efea470e595175f17 /drivers/gpu/nvgpu/include/nvgpu | |
parent | 7d6d0405311337456f50d6fa032963c18d2c9f9f (diff) |
gpu: nvgpu: fix TSG enable sequence
Due to a h/w bug in Maxwell and Pascal we first need to enable all channels with
NEXT and CTX_RELOAD set in a TSG, and then rest of the channels should be
enabled
Add this sequence to gk20a_tsg_enable()
Add new APIs to enable/disable scheduling of TSG runlist
gk20a_fifo_enable_tsg_sched()
gk20a_fifo_disble_tsg_sched()
Add new APIs to check if channel has NEXT or CTX_RELOAD set
gk20a_fifo_channel_status_is_next()
gk20a_fifo_channel_status_is_ctx_reload()
Bug 1739362
Change-Id: I4891cbd7f22ebc1e0bf32c52801002cdc259dbe1
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1560636
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/include/nvgpu')
4 files changed, 142 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ccsr_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ccsr_gk20a.h index 4877e4a8..c6f792e7 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ccsr_gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ccsr_gk20a.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2012-2016, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -114,6 +114,42 @@ static inline u32 ccsr_channel_status_v(u32 r) | |||
114 | { | 114 | { |
115 | return (r >> 24) & 0xf; | 115 | return (r >> 24) & 0xf; |
116 | } | 116 | } |
117 | static inline u32 ccsr_channel_status_pending_ctx_reload_v(void) | ||
118 | { | ||
119 | return 0x00000002; | ||
120 | } | ||
121 | static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void) | ||
122 | { | ||
123 | return 0x00000004; | ||
124 | } | ||
125 | static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void) | ||
126 | { | ||
127 | return 0x0000000a; | ||
128 | } | ||
129 | static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void) | ||
130 | { | ||
131 | return 0x0000000b; | ||
132 | } | ||
133 | static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void) | ||
134 | { | ||
135 | return 0x0000000c; | ||
136 | } | ||
137 | static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void) | ||
138 | { | ||
139 | return 0x0000000d; | ||
140 | } | ||
141 | static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void) | ||
142 | { | ||
143 | return 0x0000000e; | ||
144 | } | ||
145 | static inline u32 ccsr_channel_next_v(u32 r) | ||
146 | { | ||
147 | return (r >> 1) & 0x1; | ||
148 | } | ||
149 | static inline u32 ccsr_channel_next_true_v(void) | ||
150 | { | ||
151 | return 0x00000001; | ||
152 | } | ||
117 | static inline u32 ccsr_channel_busy_v(u32 r) | 153 | static inline u32 ccsr_channel_busy_v(u32 r) |
118 | { | 154 | { |
119 | return (r >> 28) & 0x1; | 155 | return (r >> 28) & 0x1; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ccsr_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ccsr_gm20b.h index 2fdf73ae..3f5d312f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ccsr_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ccsr_gm20b.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -110,6 +110,42 @@ static inline u32 ccsr_channel_status_v(u32 r) | |||
110 | { | 110 | { |
111 | return (r >> 24) & 0xf; | 111 | return (r >> 24) & 0xf; |
112 | } | 112 | } |
113 | static inline u32 ccsr_channel_status_pending_ctx_reload_v(void) | ||
114 | { | ||
115 | return 0x00000002; | ||
116 | } | ||
117 | static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void) | ||
118 | { | ||
119 | return 0x00000004; | ||
120 | } | ||
121 | static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void) | ||
122 | { | ||
123 | return 0x0000000a; | ||
124 | } | ||
125 | static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void) | ||
126 | { | ||
127 | return 0x0000000b; | ||
128 | } | ||
129 | static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void) | ||
130 | { | ||
131 | return 0x0000000c; | ||
132 | } | ||
133 | static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void) | ||
134 | { | ||
135 | return 0x0000000d; | ||
136 | } | ||
137 | static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void) | ||
138 | { | ||
139 | return 0x0000000e; | ||
140 | } | ||
141 | static inline u32 ccsr_channel_next_v(u32 r) | ||
142 | { | ||
143 | return (r >> 1) & 0x1; | ||
144 | } | ||
145 | static inline u32 ccsr_channel_next_true_v(void) | ||
146 | { | ||
147 | return 0x00000001; | ||
148 | } | ||
113 | static inline u32 ccsr_channel_busy_v(u32 r) | 149 | static inline u32 ccsr_channel_busy_v(u32 r) |
114 | { | 150 | { |
115 | return (r >> 28) & 0x1; | 151 | return (r >> 28) & 0x1; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ccsr_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ccsr_gp106.h index 65146d39..13bd4251 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ccsr_gp106.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ccsr_gp106.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -114,12 +114,40 @@ static inline u32 ccsr_channel_status_pending_ctx_reload_v(void) | |||
114 | { | 114 | { |
115 | return 0x00000002; | 115 | return 0x00000002; |
116 | } | 116 | } |
117 | static inline u32 ccsr_channel_busy_v(u32 r) | 117 | static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void) |
118 | { | 118 | { |
119 | return (r >> 28) & 0x1; | 119 | return 0x00000004; |
120 | } | ||
121 | static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void) | ||
122 | { | ||
123 | return 0x0000000a; | ||
124 | } | ||
125 | static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void) | ||
126 | { | ||
127 | return 0x0000000b; | ||
128 | } | ||
129 | static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void) | ||
130 | { | ||
131 | return 0x0000000c; | ||
132 | } | ||
133 | static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void) | ||
134 | { | ||
135 | return 0x0000000d; | ||
136 | } | ||
137 | static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void) | ||
138 | { | ||
139 | return 0x0000000e; | ||
120 | } | 140 | } |
121 | static inline u32 ccsr_channel_next_v(u32 r) | 141 | static inline u32 ccsr_channel_next_v(u32 r) |
122 | { | 142 | { |
123 | return (r >> 1) & 0x1; | 143 | return (r >> 1) & 0x1; |
124 | } | 144 | } |
145 | static inline u32 ccsr_channel_next_true_v(void) | ||
146 | { | ||
147 | return 0x00000001; | ||
148 | } | ||
149 | static inline u32 ccsr_channel_busy_v(u32 r) | ||
150 | { | ||
151 | return (r >> 28) & 0x1; | ||
152 | } | ||
125 | #endif | 153 | #endif |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ccsr_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ccsr_gp10b.h index 99398961..33c83c80 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ccsr_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ccsr_gp10b.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -110,6 +110,42 @@ static inline u32 ccsr_channel_status_v(u32 r) | |||
110 | { | 110 | { |
111 | return (r >> 24) & 0xf; | 111 | return (r >> 24) & 0xf; |
112 | } | 112 | } |
113 | static inline u32 ccsr_channel_status_pending_ctx_reload_v(void) | ||
114 | { | ||
115 | return 0x00000002; | ||
116 | } | ||
117 | static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void) | ||
118 | { | ||
119 | return 0x00000004; | ||
120 | } | ||
121 | static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void) | ||
122 | { | ||
123 | return 0x0000000a; | ||
124 | } | ||
125 | static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void) | ||
126 | { | ||
127 | return 0x0000000b; | ||
128 | } | ||
129 | static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void) | ||
130 | { | ||
131 | return 0x0000000c; | ||
132 | } | ||
133 | static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void) | ||
134 | { | ||
135 | return 0x0000000d; | ||
136 | } | ||
137 | static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void) | ||
138 | { | ||
139 | return 0x0000000e; | ||
140 | } | ||
141 | static inline u32 ccsr_channel_next_v(u32 r) | ||
142 | { | ||
143 | return (r >> 1) & 0x1; | ||
144 | } | ||
145 | static inline u32 ccsr_channel_next_true_v(void) | ||
146 | { | ||
147 | return 0x00000001; | ||
148 | } | ||
113 | static inline u32 ccsr_channel_busy_v(u32 r) | 149 | static inline u32 ccsr_channel_busy_v(u32 r) |
114 | { | 150 | { |
115 | return (r >> 28) & 0x1; | 151 | return (r >> 28) & 0x1; |