gpu: nvgpu: add tsg_id to vgpu_gr_ctx struct

To reuse linux gr code for QNX tsg_id will be required during alloc_gr_ctx.
rm-server will reuse the gr_ctx from tsg and would not allocate it.

Jira VQRM-2982

Change-Id: I236deb181b89a38e70dedca4190a4275be9f0b28
Signed-off-by: Shashank Singh <shashsingh@nvidia.com>
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1659907
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Sourab Gupta <sourabg@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 1 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h
index a7a877ff..c269dc24 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h
@@ -369,6 +369,7 @@ struct tegra_vgpu_gr_ctx_params {
         u64 as_handle;
         u64 gr_ctx_va;
         u32 class_num;
+        u32 tsg_id;
 };
 
 struct tegra_vgpu_channel_bind_gr_ctx_params {