diff options
author | Vaikundanathan S <vaikuns@nvidia.com> | 2018-04-25 03:34:49 -0400 |
---|---|---|
committer | Tejal Kudav <tkudav@nvidia.com> | 2018-06-14 09:44:06 -0400 |
commit | 74ceef1230f414956aceaa027580c6f71fe42153 (patch) | |
tree | 650294c53ff2daf198f83d1f2da50785b10fa17b /drivers/gpu/nvgpu/include/nvgpu/pmuif | |
parent | 440cda8a6797a0c8c423a5e3357a458ed4dfad07 (diff) |
gpu:nvgpu: Update vfe_load for GV100
Add gops to choose vfe_load between GP and GV.
Bug 200399373
Change-Id: I73e0fbd2f1956e81c241f09639c69f33082e617b
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1702143
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/include/nvgpu/pmuif')
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperf.h | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperf.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperf.h index 83d08afc..aedf7988 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperf.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperf.h | |||
@@ -37,6 +37,34 @@ | |||
37 | #define NV_PMU_PERF_CMD_ID_BOARDOBJ_GRP_SET (0x00000003) | 37 | #define NV_PMU_PERF_CMD_ID_BOARDOBJ_GRP_SET (0x00000003) |
38 | #define NV_PMU_PERF_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000004) | 38 | #define NV_PMU_PERF_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000004) |
39 | 39 | ||
40 | /*! | ||
41 | * RPC calls serviced by PERF unit. | ||
42 | */ | ||
43 | #define NV_PMU_RPC_ID_PERF_BOARD_OBJ_GRP_CMD 0x00 | ||
44 | #define NV_PMU_RPC_ID_PERF_LOAD 0x01 | ||
45 | #define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_INFO_GET 0x02 | ||
46 | #define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_INFO_SET 0x03 | ||
47 | #define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_SET_CONTROL 0x04 | ||
48 | #define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_QUEUE_CHANGE 0x05 | ||
49 | #define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_LOCK 0x06 | ||
50 | #define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_LOAD 0x07 | ||
51 | #define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_QUERY 0x08 | ||
52 | #define NV_PMU_RPC_ID_PERF_PERF_LIMITS_INVALIDATE 0x09 | ||
53 | #define NV_PMU_RPC_ID_PERF_VFE_EQU_EVAL 0x0A | ||
54 | #define NV_PMU_RPC_ID_PERF_VFE_INVALIDATE 0x0B | ||
55 | #define NV_PMU_RPC_ID_PERF_VFE_EQU_MONITOR_SET 0x0C | ||
56 | #define NV_PMU_RPC_ID_PERF_VFE_EQU_MONITOR_GET 0x0D | ||
57 | #define NV_PMU_RPC_ID_PERF__COUNT 0x0E | ||
58 | /* | ||
59 | * Defines the structure that holds data | ||
60 | * used to execute LOAD RPC. | ||
61 | */ | ||
62 | struct nv_pmu_rpc_struct_perf_load { | ||
63 | /*[IN/OUT] Must be first field in RPC structure */ | ||
64 | struct nv_pmu_rpc_header hdr; | ||
65 | u32 scratch[1]; | ||
66 | }; | ||
67 | |||
40 | struct nv_pmu_perf_cmd_set_object { | 68 | struct nv_pmu_perf_cmd_set_object { |
41 | u8 cmd_type; | 69 | u8 cmd_type; |
42 | u8 pad[2]; | 70 | u8 pad[2]; |