gpu: nvgpu: falcon queue support

-Renamed "struct pmu_queue" to "struct
 nvgpu_falcon_queue" & moved to falcon.h
-Renamed pmu_queue_* functions to flcn_queue_* &
 moved to new file falcon_queue.c
-Created ops for queue functions in struct
 nvgpu_falcon_queue to support different queue
 types like DMEM/FB-Q.
-Created ops in nvgpu_falcon_engine_dependency_ops
 to add engine specific queue functionality & assigned
 correct HAL functions in hal*.c file.
-Made changes in dependent functions as needed to replace
 struct pmu_queue & calling queue functions using
 nvgpu_falcon_queue data structure.
-Replaced input param "struct nvgpu_pmu *pmu" with
 "struct gk20a *g" for pmu ops pmu_queue_head/pmu_queue_tail
 & also for functions gk20a_pmu_queue_head()/
 gk20a_pmu_queue_tail().
-Made changes in nvgpu_pmu_queue_init() to use nvgpu_falcon_queue
 for PMU queue.
-Modified Makefile to include falcon_queue.o
-Modified Makefile.sources to include falcon_queue.c

Change-Id: I956328f6631b7154267fd5a29eaa1826190d99d1
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1776070
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 2 insertions, 26 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmu.h
index 507b8133..4d1bf75a 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/pmu.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmu.h
@@ -32,6 +32,7 @@
 #include <nvgpu/nvgpu_common.h>
 #include <nvgpu/flcnif_cmn.h>
 #include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
+#include <nvgpu/falcon.h>
 
 #define nvgpu_pmu_dbg(g, fmt, args...) \
         nvgpu_log(g, gpu_dbg_pmu, fmt, ##args)
@@ -266,30 +267,6 @@ struct pmu_ucode_desc_v1 {
         u32 compressed;
 };
 
-struct pmu_queue {
-
-        /* used by hw, for BIOS/SMI queue */
-        u32 mutex_id;
-        u32 mutex_lock;
-        /* used by sw, for LPQ/HPQ queue */
-        struct nvgpu_mutex mutex;
-
-        /* current write position */
-        u32 position;
-        /* physical dmem offset where this queue begins */
-        u32 offset;
-        /* logical queue identifier */
-        u32 id;
-        /* physical queue index */
-        u32 index;
-        /* in bytes */
-        u32 size;
-
-        /* open-flag */
-        u32 oflag;
-        bool opened; /* opened implies locked */
-};
-
 struct pmu_mutex {
         u32 id;
         u32 index;
@@ -345,7 +322,7 @@ struct nvgpu_pmu {
 
         struct pmu_sha1_gid gid_info;
 
-        struct pmu_queue queue[PMU_QUEUE_COUNT];
+        struct nvgpu_falcon_queue queue[PMU_QUEUE_COUNT];
 
         struct pmu_sequence *seq;
         unsigned long pmu_seq_tbl[PMU_SEQ_TBL_SIZE];
@@ -450,7 +427,6 @@ int nvgpu_pmu_mutex_release(struct nvgpu_pmu *pmu, u32 id, u32 *token);
 
 int nvgpu_pmu_queue_init(struct nvgpu_pmu *pmu, u32 id,
         union pmu_init_msg_pmu *init);
-bool nvgpu_pmu_queue_is_empty(struct nvgpu_pmu *pmu, struct pmu_queue *queue);
 
 /* send a cmd to pmu */
 int nvgpu_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd,