gpu: nvgpu: remove unused register accessors for volta

Remove some unused register/field accessors for gv100/gv11b since they are not
being accessed anymore on these chips

Bug 2173122

Change-Id: Ia4692a72e23024d2ee71a80b08040885af21a9ef
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1830312
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

6 files changed, 1 insertions, 89 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h
index ac936181..4e9b590b 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h
@@ -528,24 +528,4 @@ static inline u32 fifo_cfg0_pbdma_fault_id_v(u32 r)
 {
         return (r >> 16U) & 0xffU;
 }
-static inline u32 fifo_fb_iface_r(void)
-{
-        return 0x000026f0U;
-}
-static inline u32 fifo_fb_iface_control_v(u32 r)
-{
-        return (r >> 0U) & 0x1U;
-}
-static inline u32 fifo_fb_iface_control_enable_f(void)
-{
-        return 0x1U;
-}
-static inline u32 fifo_fb_iface_status_v(u32 r)
-{
-        return (r >> 4U) & 0x1U;
-}
-static inline u32 fifo_fb_iface_status_enabled_f(void)
-{
-        return 0x10U;
-}
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h
index fb558d2f..cf406c34 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h
@@ -256,24 +256,4 @@ static inline u32 mc_enable_pb_sel_f(u32 v, u32 i)
 {
         return (v & 0x1U) << (0U + i*1U);
 }
-static inline u32 mc_elpg_enable_r(void)
-{
-        return 0x0000020cU;
-}
-static inline u32 mc_elpg_enable_xbar_enabled_f(void)
-{
-        return 0x4U;
-}
-static inline u32 mc_elpg_enable_pfb_enabled_f(void)
-{
-        return 0x100000U;
-}
-static inline u32 mc_elpg_enable_hub_enabled_f(void)
-{
-        return 0x20000000U;
-}
-static inline u32 mc_elpg_enable_l2_enabled_f(void)
-{
-        return 0x8U;
-}
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h
index a5c8dad3..41d7d1b6 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h
@@ -336,10 +336,6 @@ static inline u32 pbdma_config_l2_evict_normal_f(void)
 {
         return 0x1U;
 }
-static inline u32 pbdma_config_l2_evict_last_f(void)
-{
-        return 0x2U;
-}
 static inline u32 pbdma_config_ce_split_enable_f(void)
 {
         return 0x0U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h
index cb8bf611..9ec30bf9 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h
@@ -664,24 +664,4 @@ static inline u32 fifo_cfg0_pbdma_fault_id_v(u32 r)
 {
         return (r >> 16U) & 0xffU;
 }
-static inline u32 fifo_fb_iface_r(void)
-{
-        return 0x000026f0U;
-}
-static inline u32 fifo_fb_iface_control_v(u32 r)
-{
-        return (r >> 0U) & 0x1U;
-}
-static inline u32 fifo_fb_iface_control_enable_f(void)
-{
-        return 0x1U;
-}
-static inline u32 fifo_fb_iface_status_v(u32 r)
-{
-        return (r >> 4U) & 0x1U;
-}
-static inline u32 fifo_fb_iface_status_enabled_f(void)
-{
-        return 0x10U;
-}
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h
index bff73076..a1bf15bd 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -228,24 +228,4 @@ static inline u32 mc_enable_pb_sel_f(u32 v, u32 i)
 {
         return (v & 0x1U) << (0U + i*1U);
 }
-static inline u32 mc_elpg_enable_r(void)
-{
-        return 0x0000020cU;
-}
-static inline u32 mc_elpg_enable_xbar_enabled_f(void)
-{
-        return 0x4U;
-}
-static inline u32 mc_elpg_enable_pfb_enabled_f(void)
-{
-        return 0x100000U;
-}
-static inline u32 mc_elpg_enable_hub_enabled_f(void)
-{
-        return 0x20000000U;
-}
-static inline u32 mc_elpg_enable_l2_enabled_f(void)
-{
-        return 0x8U;
-}
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h
index 75bdae1c..c04d30a4 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h
@@ -336,10 +336,6 @@ static inline u32 pbdma_config_l2_evict_normal_f(void)
 {
         return 0x1U;
 }
-static inline u32 pbdma_config_l2_evict_last_f(void)
-{
-        return 0x2U;
-}
 static inline u32 pbdma_config_ce_split_enable_f(void)
 {
         return 0x0U;