gpu: nvgpu: Initialize hwpm perfmons (engine_sel)

- For Mode-E ctxsw it is required that engine_sel
is set to 0xFFFFFFFF.
- Default 0 is a valid signal and causes problems.

Bug 2106999

Change-Id: I5cdb4441a8e6d7e8133c31a9e361b54611dd2995
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1770755
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 24 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h
index 268efc52..a7ba460e 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h
@@ -232,4 +232,28 @@ static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void)
 {
         return 0x10U;
 }
+static inline u32 perf_pmmsys_engine_sel_r(u32 i)
+{
+        return 0x0024006cU + i*512U;
+}
+static inline u32 perf_pmmsys_engine_sel__size_1_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 perf_pmmfbp_engine_sel_r(u32 i)
+{
+        return 0x0020006cU + i*512U;
+}
+static inline u32 perf_pmmfbp_engine_sel__size_1_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 perf_pmmgpc_engine_sel_r(u32 i)
+{
+        return 0x0018006cU + i*512U;
+}
+static inline u32 perf_pmmgpc_engine_sel__size_1_v(void)
+{
+        return 0x00000020U;
+}
 #endif