gpu: nvgpu: Remove falcon header usage in nvlink

For nvlink, we need to use minion registers instead of
generic falcon registers.

JIRA NVGPU-966

Change-Id: I850d2e2a4475394c37d2253c5034713c78439bd0
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1795086
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 16 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_minion_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_minion_gv100.h
index a57ea97a..e4bbf23f 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_minion_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_minion_gv100.h
@@ -104,6 +104,22 @@ static inline u32 minion_falcon_irqstat_halt_v(u32 r)
 {
         return (r >> 4U) & 0x1U;
 }
+static inline u32 minion_falcon_irqstat_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 minion_falcon_irqstat_exterr_v(u32 r)
+{
+        return (r >> 5U) & 0x1U;
+}
+static inline u32 minion_falcon_irqstat_exterr_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 minion_falcon_irqstat_exterr_true_f(void)
+{
+        return 0x20U;
+}
 static inline u32 minion_falcon_irqmask_r(void)
 {
         return 0x00000018U;