diff options
author | David Ung <davidu@nvidia.com> | 2020-04-24 20:13:11 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2020-05-22 01:54:27 -0400 |
commit | b7fb70db759af82fb03988d4c224892df236ac73 (patch) | |
tree | 6dda27c4cd7d2dc5db75239145955804a154e3e1 /drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h | |
parent | dfab7cc86acdc26c3705551740c55b4d4898587a (diff) |
gpu: nvgpu: Updated with generator headers
Add pmu_idle_mask_1, pmu_idle_mask_2 and pmu_idle_mask_2_supp
Bug 2833620
Change-Id: Icceb99b48a227d32653fd9fbc3da9e27065e9fe2
Signed-off-by: David Ung <davidu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2334219
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h')
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h index 03affe8e..1cda12de 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h | |||
@@ -840,6 +840,14 @@ static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void) | |||
840 | { | 840 | { |
841 | return 0x200000U; | 841 | return 0x200000U; |
842 | } | 842 | } |
843 | static inline u32 pwr_pmu_idle_mask_1_r(u32 i) | ||
844 | { | ||
845 | return 0x0010aa34U + i*8U; | ||
846 | } | ||
847 | static inline u32 pwr_pmu_idle_mask_2_r(u32 i) | ||
848 | { | ||
849 | return 0x0010a840U + i*4U; | ||
850 | } | ||
843 | static inline u32 pwr_pmu_idle_count_r(u32 i) | 851 | static inline u32 pwr_pmu_idle_count_r(u32 i) |
844 | { | 852 | { |
845 | return 0x0010a508U + i*16U; | 853 | return 0x0010a508U + i*16U; |
@@ -936,6 +944,10 @@ static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i) | |||
936 | { | 944 | { |
937 | return 0x0010a9f4U + i*8U; | 945 | return 0x0010a9f4U + i*8U; |
938 | } | 946 | } |
947 | static inline u32 pwr_pmu_idle_mask_2_supp_r(u32 i) | ||
948 | { | ||
949 | return 0x0010a690U + i*4U; | ||
950 | } | ||
939 | static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i) | 951 | static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i) |
940 | { | 952 | { |
941 | return 0x0010aa30U + i*8U; | 953 | return 0x0010aa30U + i*8U; |