gpu: nvgpu: Regenerated headers

Regenerating header from register generator

Bug 2833620

Change-Id: Idc8e922bb611ed5acae66b6ca38db4bb9c8a1904
Signed-off-by: David Ung <davidu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2335263
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 2 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
index 01dc99d5..f7d8089d 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
@@ -4978,11 +4978,11 @@ static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void)
 }
 static inline u32 gr_gpcs_pri_mmu_ctrl_atomic_capability_mode_m(void)
 {
-        return U32(0x3U) << 24U;
+        return 0x3U << 24U;
 }
 static inline u32 gr_gpcs_pri_mmu_ctrl_atomic_capability_sys_ncoh_mode_m(void)
 {
-        return U32(0x1U) << 27U;
+        return 0x1U << 27U;
 }
 static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void)
 {